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LMK04131: stability when input frequency is out of the lock range

Part Number: LMK04131
Other Parts Discussed in Thread: LMK05028

Hello,

in our application dedicated to digital audio, we need to generate a clean master clock at 24.576MHz with a crystal. We have also the need to syncronize the generated clock with an external source at the same frequency. We need to syncronize the internal generated clock only if the external clock frequency is within +- 100ppm.

For this application we see the LMK0431, our need is to have at the output a 24.576MHz clock signal uninterrupted also if  the external source is present or not or during transition between on or off.

Another task is the stability of the output frequency if the external signal frequency is outside the lock range of the pll1, for example if the external frequency is 24.000 MHz. What happens in this condition? The output frequency is stable or pll1 is moving trying to lock to a reference out of the lock range?

Many thanks,

Enzo

  • Hi Enzo,
    LMK04131 is a cascaded PLL jitter cleaner. PLL1 would adopt a VCXO, which has a frequency pulling range, for example +/- 100ppm.
    When input reference is lost, or changed too much (24.576 MHz -- > 24.000 MHz, delta is over 100 ppm), PLL1 would unlock. LMK04131 didn't have holdover function, voltage on VCXO ctrl pin would be 0V or 3.3V, and VCXO output on max ( +100ppm) or min (-100ppm) frequency. If reference frequency is only changed in VCXO range (+/-100ppm), then output frequency would follow input reference.

    Because VCXO always runs, output 24.576 MHz is not uninterrupted when reference is changed. But it is possible that there is a output phase jump in the transition from status locked to unlocked, then to locked again. How much phase jump system could tolerate? We could design narrow loop filter for PLL1 and proper VCXO to satisfy the target.

    Regards,
    Shawn
  • Hi Shawn, thank you very much for your answer,

    the generated clock at 24.576MHz will be the master clock for a professional digital audio system driving A/D and D/A converters so, we can't accept too much jitter in the clock signal. TI has other clock generators / jitter cleaner with the holdover function?

    Regards,

    Enzo

  • Hi Enzo,
    In your application, DPLL should be considered to achieve the best holdover performance. TI would release a DPLL LMK05028 by this year, which has 4 input reference and 8 outputs, holdover or hitless switch could achieve 10ps level (vs. competitor's 100ps or 10ns). If your project schedual is very urgent, other vendors also could provide alternative DPLL products.

    Regards,

    Shawn