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LMK04616: Multiple JESD204B Clock Distributors

Part Number: LMK04616
Other Parts Discussed in Thread: LMK04610

Hi,

I need to distribute twelve device clock and SYSREF signals in my system (to DACs, ADCs and FPGA). 

The part with the highest count of clock outputs i saw is the LMK04616 which has sixteen clock outputs (eight device clock and eight SYSREF signals).

Still, i am four clocks short. What is the best way of using several JESD204B compliant clock distributors and still guarantee deterministic relationship between 

all SYSREFs and device clocks in the system?

Thanks in advance,

Guy. 

  • Hello Vaisman,

    You can use 2xLMK04616 or 1x LMK04610 and 1x LMK04616 and use the multi device configuration t have deterministic SYSREF & DEVCLKs.
    You can refer to following App note for more information:

    www.ti.com/.../snau222

    Best regards
    Puneet
  • Hi Puneet,

    Thank you for the application note - it is very helpful.

    I would like to use configuration 4 with a few a changes:
    - Device 1 will be in 'PLL2 only low skew mode'.
    - Device 1 will output a pulsed sysref to sync pin of device 2 and 3 separably (through different CLKout pins).

    Will this still configuration still work?

    Also,
    - Is there a specif reason OSCin of device 2 and 3 are fed with a continuous sysref and not a device clock?
    - Is it possible to a drive a single ended load with CLKout and not use a differential to single ended buffer?

    Thanks,
    Guy.
  • Hello Guy

    Sorry for the late reply,below are my comments:

    - Device 1 will be in 'PLL2 only low skew mode'.
    - Device 1 will output a pulsed sysref to sync pin of device 2 and 3 separably (through different CLKout pins).

    Will this still configuration still work?
    A: Yes, that sould be fine.

    Also,
    - Is there a specif reason OSCin of device 2 and 3 are fed with a continuous sysref and not a device clock?
    A: If device clock is used instead of continuous SYSREF, The SYSREF dividers from two devices will not be aligned at each power up relative to each other, although all clocks from single device will be aligned.
    - Is it possible to a drive a single ended load with CLKout and not use a differential to single ended buffer?
    A: Yes, if the single ended clock output meets the VIL/VIH levels of the buffer, it can be used.

    Best regards
    Puneet