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LMK04616: Some Question about LMK04616

Sho Ogane
Genius 5575 points
Part Number: LMK04616

Hi all.

I have some question about LMK04616, so please help me.

1. What are C4, R4 at PLL2? For 4rd Filter? I could not find the explanation in datasheet.

2. Register 0xAF and 0xB0, I want to know enable status.
    Which is bit that PLL2_RDIV_CLKEN is enable, 0 or 1? I think enable bit is 1
    Which is bit that PLL2_NDIV_CLKEN is enable, 0 or 1? I think enable bit is 0

3. Please tell me the setting range of PLL2_LD_WNDW_SIZE and PLL2_LD_WNDW_SIZE_INITIAL?
    I can't understand the 0x85 and 0x86 register, Is 0x01 setting 2ns?  If we write 0x3F, can we set 62ns?
    Please tell me the relationship of register and windows size. 

4. Please tell me the difference of Soft reset and SWRST. What is SWRST?

Sorry for many question, but I would like to get your comment as soon as possible.

Best Regards,
Sho

  • 0
    TI__Expert 5370 points
    Dear Sho, I have sent on note to a colleague to follow up with your question, thank you for your patience. Regards, Simon.
  • 0 in reply to Simon Damphousse
    Genius 5575 points
    Hi Simon san

    Thank you for your reply. Ok I am waiting your comment.

    Best Regards,
    Sho
  • 0
    TI__Expert 8865 points
    Hi Sho
    Here are the answers to your questions:

    1. What are C4, R4 at PLL2? For 4rd Filter? I could not find the explanation in datasheet.
    A: Registers 0x70 & 0x71 has no functions. Thanks for binging it to our attention. I will update that in the datasheet.
    It is only possible to add 3rd order pole to the PLL2 as explained in the datasheet section "9.3.5.2.4 PLL2 3rd Order Loop Filter"

    2. Register 0xAF and 0xB0, I want to know enable status.
    Which is bit that PLL2_RDIV_CLKEN is enable, 0 or 1? I think enable bit is 1
    Which is bit that PLL2_NDIV_CLKEN is enable, 0 or 1? I think enable bit is 0
    A: Those bits enables the clocks to the NDIV & RDIV. They are active High, that means logic 1 will enable the clock.

    3. Please tell me the setting range of PLL2_LD_WNDW_SIZE and PLL2_LD_WNDW_SIZE_INITIAL?
    I can't understand the 0x85 and 0x86 register, Is 0x01 setting 2ns? If we write 0x3F, can we set 62ns?
    Please tell me the relationship of register and windows size.
    A: Window size for PLL2 is from 1ns to 10ns, 0x00 is 1ns and 0x01 is 2ns. PLL2_LD_WNDW_SIZE_INITIAL is used for initial calibration. You can set PLL2_LD_WNDW_SIZE & PLL2_LD_WNDW_SIZE_INITIAL both to the same value.

    4. Please tell me the difference of Soft reset and SWRST. What is SWRST?
    A: Soft reset is SWRST.
    Software Reset: Writing a 1 to SWRST will reset the device apart from the SPI programmable registers. SWRST is automatically cleared to 0.

    Don't hesitate to contact if you have further questions.
    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Genius 5575 points

    Hi Puneet san

    Thank you for your reply. I understood your answer. I have more question about DC clock wave. The waveform is confidential information. So I will send the e-mail. Please check the e-mail.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Puneet-san

    Thank you for your support. I have more question about LMK04616. So Please check my question. 
    1. You recommend to click SWRST(=Soft Reset) high in TICSPro when all supplies is powered up. Sorry please tell me the  detail function of Soft Reset again. 


    2.0x6B is PLL_RC_CLK_DIV. What is RC Clk? in addition, What is PLL_F_30(0x54)? I don't know which I should choice PLL RC Freq 0 or PLL RC Freq 1.

    And I sent you the e-mail about DC clock issue, so please check it too.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Expert 8865 points
    Hi Sho,
    Writing High to SOFT reset will reset the device but registers should stay programmed.
    Is there a specific reason for using the soft reset?
    Are they not using RESETN pin?

    Regarding your second question, There is no need to use PLL_RC_CLK_DIV, PLL_F_30 etc. The function of those bits was to enable the regulation in the DAC & charge pumps inside the PLL1. But we have seen that there is no need to have this regulation enabled. Enabling those functions will generate more noise from the PLL1 and degrade the overall phase noise in <1kHz offset region.
    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Genius 5575 points

    Hi Puneet-san

    Thank you for your support. I confirm about RESETN to my customer.

    Regarding second answer, I understood, thank you very much.

    Sorry, I have other question. When my customer load the custom file(.tcs) and all register is set in TICSPro, I confirm the GUI Reset PLL1_RDIV_SWRST、PLL1_NDIV_SWRST.
    Do we need to reset those divider? And is it no problem PLL_RDIV_SWRST to reset one time by every CLKINx? 
    I am curious whether it is necessary to reset multiple times.

    Best Regards, 
    Sho

  • 0 in reply to Sho Ogane
    TI__Expert 8865 points
    Hi Sho
    There is no need to reset the PLL1_RDIV & PLL1_NDIV. They are automatically reset during the startup sequence. You need to reset only if you change the divider values on the fly.
    Best regards
    Puneet
  • 0 in reply to Puneet Sareen
    Genius 5575 points

    Hi Puneet-san

    Thank you very much for your support.

    I have one more question about RESETN button in TICSpro.
    I attach the file, so please confirm it and check whether it can be reproduced with actual machine.

    Best Regards,
    Sho

    TICSpro issue.pdf