LMK04616: Phase Noise data

Ayesha fakruddin

Part Number: LMK04616

Hi,

We are operating LMK04616 in single PLL(PLL2) mode. The reference clock input to LMK shall be from a low noise TCXO. Please provide the Phase noise at output clock

105MHz

The reference clock phase noise is as mentioned below. Carrier frequency, 100MHz and offset frequency in Hz:-

100, -107
1000, -130
10000, -148
100000, -151
1000000, -155

The configuration is as shown below:-

over 6 years ago

0 Patrick Kammermayer over 6 years ago

TI__Expert 5325 points

Hello Ayesha,
can you please check your upload of the configuration? It seems this did not work.
Do you have specific bandwidth requirements for the PLL?
Can you please also share your target specification, so our expert in the team could tweak the configuration when necessary?

Best regards,
Patrick

0 Ayesha fakruddin over 6 years ago in reply to Patrick Kammermayer

Intellectual 360 points

The requirement is as follows
Input (CLKin0): LVDS 100MHz
Outputs Req: 105MHz and 10.5MHz
Target PLL loop bandwidth: 200kHz (to be decided based on VCO phase noise. Can be modified)
Mode of operation : PLL2 only mode
VCO frequency : 5880MHz
PFD frequency : 10MHz

Need to get the phase noise plot @ 105MHz and 10.5MHz