LMK04616: Phase Noise data

Hi,

We shall be using LMK series devices in clock generation (PLL 2 only Mode) and distribution mode to generate the below mentioned clocks:

• LMK04616 - 105MHz and 10.5 MHz
• LMK04610 - 90MHz and 9 MHz
• LMK04610 - 80 MHz and 8MHz

Please let me know the output clock phase noise and what would be the optimum loop filter bandwidth to generate 105, 90 and 80MHz (depends on the VCO phase noise).

The input clock to all the above devices shall be from a 100MHz TCXO with phase noise of:

• -112dBc/Hz @ 100Hz offset
• -135dBc/Hz @ 1KHz offset
• -152dBc/Hz @ 10KHz offset
• -160dBc/Hz @ 100KHz offset
• -165dBc/Hz @ 1000KHz offset

Also please let me know when would the simulation model be available for LMK04616/0

Regards,

Ayesha