Hi,
We are designing LMK04610 in single PLL2 mode with PLL1 bypass. the input to LMK is a 100MHz differential LVDS input to CLKin0 port. The requirement is to generate 3 otputs of 90MHz and 4 outputs of 9MHz (Sysref signals). The PFD frequency is 10MHz and the VCO frequency is configured to 5850 MHz. The N divider value shall be 117.
For the above mentioned settings, the PLL2 loop bandwidth calculated by the tool is >10 MHz. Please clarify if this is a tool issue or configuration issue.
Regards,
Ayesha