LMK04828: LMK04828 PLL issue?

Hello Henry,

When you say CLKin is 30.72 MHz, is that a noisy clock or the TCXO TG5032?  I think it is some noisy clock?

You mention OSCin is 30.72 MHz, I assume that you were planning to use the VC-TCXO option of the TG5032.

I would recommend downloading the clockdesigntool software (www.ti.com/.../clockdesigntool) and typing your input requirements of 30.72 MHz, 30.72 MHz VCXO (which would be your TC-VCXO), and at least one output - like 491.52 MHz.
This will allow you to find LMK04828 as a solution.

In the CDT you can load a noise profile for your reference and TC-VCXO for improved simulation.  By default the tool designs optimum loop bandwidth solutions with with maximum possible phase detector frequencies.  (Refer to the choosing PLL loop bandwidths presentation in the E2E files section).

Without knowing more about your system such as the nature of the reference clock, for PLL1 I recommend designing the loop filter as:

• Updating the PLL1 phase detector frequency to ~1 MHz.
• Designing the loop filter for 50 Hz phase margin & 100 Hz loop bandwidth.  You could decrease or increase loop bandwidth as desired.
• You could reduce the PLL1 charge pump current if the C2 capacitor is too large.
• Using this tool you can also see the final output performance.

It is possible to do this design with clock architect, however it is a bit more difficult to ensure your VCXO frequency is 30.72 MHz, see the attached document on using the Clock Architect Tool.

About PLL2 loop filter design, if you set the PLL2 R = 0.5, it will result in using the doubler and your PLL2 phase noise performance will improve.

7673.Using Clock Architect for Dual Loop PLLs - in dual and single loop mode, 2017-03-21.pdf

Note for both CDT and Clock Architect the LMK04828 profile does not implement the SYSREF divider.  So if you type a low frequency, it will not find a solution. 

Also, you mentioned 100 MHz to 491.52 MHz.  The LMK04828 has integer output dividers, so you wouldn't be able to get 100 MHz and 491.52 MHz at the same time.  You can do 122.88 MHz and 491.52 MHz no problem, but the 100 MHz would be an issue.  If you did need 100 MHz and you are using a 30.72 MHz VCXO, then your performance would be hurt because the PLL2 phase detector frequency would be 960 kHz (assuming 2949.12 MHz VCO frequency).  This may result in need for alternate PLL2 loop filter design for optimum performance... which would not be as good as with a 30.72 MHz or 61.44 MHz PLL2 phase detector frequency.

73,
Timothy