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LMK04616: LVDS CLKInx inputs

Harry Ramaker
Prodigy 50 points
Part Number: LMK04616

LMK04616_LVDS.docx

In the LMK04616 datasheet is stated that the minimal input swing of the CLKInx must be 400mV. The LVDS standard is 350mV. How does that work with the LMK04616 part?

According the datasheet the LMK04616 must be able to accept LVDS (Figure 19 datasheet).

  • 0
    TI__Mastermind 30410 points

    Hello Harry,

    The parameter specified in the LMK04616 datasheet is VID,PP, which is defined as 2 x VID (see figure 9). VOD,PP of ZL40213 is defined as 2 x VOD (see figure 19 in ZL40213 datasheet). So the minimum ZL40213 LVDS VOD,PP = 500 mV, which meets the LMK04616 VID,PP spec.

    In the notes you attached, you mentioned that if the swing on CLKinX is too low, PLL1 will not lock. With an explanation of the VID and VID,PP difference, can you please confirm whether the input signal is within datasheet specifications when PLL1 will not lock? There is also a minimum slew rate requirement for clock inputs to the LMK04616, so can you please confirm your test signal obeys the slew rate requirement as well? The ZL40213 claims a minimum LVDS slew rate of 0.55 V/ns, which meets the LMK04616 differential slew rate spec.

    Regards,