CDCE62005: Timing requirements between SPI_LE and Powerdown

Hi,everyone

According to the document： SPI_LE has to be logic "1 " before the Power_Down pin toggles low-to-high in order for the EEPROM to load properly.

so，(1)Is there a minimum time requirement between SPI_LE and power_down?

       (2)SPI_LE and power_down to be logic "1 " at the same time，OK？

Thanks.