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CDCE62005: U1-U4 Clock Outputs affected by access to registers of U0 Port

user5861959
Prodigy 20 points
Part Number: CDCE62005
Other Parts Discussed in Thread: LMK03318, CDCE6214-Q1

Problem: 
We have programmed the CDCE's internal clock source to be 1 GHz (default from the reference design and set up by the FPGA). We're only changing the independent output divider for each output. 
By design, each output port of the clock generator should be (and must be) independent from each other. So if our SW changes the output divider ratio of Port 0, it should not affect the other 4 outputs.

But the reality is: it does affect the other 4 outputs, and the outcome is quite serious: When Port 1 (U1) is disturbed while we change port 0, the SGMII link between MAC and PHY is broken, causing the DSP to lose connection with the PC, other Ports (U2-U4) are also affected by changes of the output divider ratio of Port 0.  

It's the mere action of writing to the CDCE registers that is causing the issue, apparently. If I just try to turn off Port 0, it will also cause disturbance to other ports. Even writing the same data to the same register causes disturbance to other ports. So it's not output frequency change, it's just the mere access to port register, that is causing instability to outputs of other ports.

I would like to know what factor may cause this issue, or if it's possible that the CDCE62005 chipset currently used is a defective one or damaged one?

Thank you.

Stanley

  • 0
    TI__Mastermind 18070 points

    Hi Stanley,

    You are right that changes on one channel shouldn't affect others and what you saw is definitely not expected. Can you narrow down the problem by observing what changes happen to other channels when one channel is programmed. Do they have glitches, change of frequency / amplitude or something else?

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 20 points

    Hi Hao, thanks for your comments and suggestions, we didn't directly test the frequency and amplitude or signal output from other ports when making divider change of U0, we just performed some experiments, by just writing any data to a register inside the CDCE chip will disturb the chip, causing it to declare PLL unlock. Even by writing the same data to the same register will cause problems. The register can be associated with any output port. So this clock generator is hopelessly unable to handle any changes at run time. We will have to use another external divider to handle this clock signal output from U0 to meet our application.

    Regards!

    Stanley

  • 0 in reply to user5861959
    TI__Mastermind 18070 points

    Hi Stanley,

    That's unfortunate. I didn't try this myself in the lab, but I didn't find "glitchless" feature in the datasheet, meaning that it may be true that it doesn't support glitchless output divider changes. You probably need clock generators that are glitch free when output dividers are changed, such as CDCE6214-Q1 and LMK03318.

    Regards,
    Hao