CDCLVC1106: Application question

user4979999

Part Number: CDCLVC1106

Hi,

Customer would like to use our clock buffer for Intel ethernet chip I210, and Intel reference circuit has two cap C1/C2, is that ok to put these cap at our buffer output? Will it impact our buffer performance?

Regards,

Lynn

over 4 years ago

0 Lane Boyd over 4 years ago

TI__Genius 16845 points

Hi Lynn,

47pF load may significantly slow down the edges, and the operating frequency could pose further limitation depending on the edge rate. Could you measure the performance and verify it meets the requirements?

Kind regards,
Lane

Clock & timing

Clock & timing forum

CDCLVC1106: Application question