Other Parts Discussed in Thread: LMK05028
Hello,
I'm developing a device including ADC/DACs and FPGA which will use an external reference for synchronization between multiple devices.
The key point is to use both frequency and phase of input signal to achieve sample synchronization, possibly with internal phase correction, to be able to fine align devices using test signals.
Sampling board will include a JESD clock cleaner / generator with zero-delay mode (e.g. LMK0482x) adding a feedback from output after divisors, so alignment between input and SYSREF can be granted.
External reference however could be:
- 10MHz = this signal could be fed directly to JESD clock cleaner / generator
- 1Hz (PPS) = as frequency is low, a network clock recovery device should be added, however should include zero-delay mode to preserve phase
I identified LMK05318, which should be able to recover a clean 10MHz from possibly jittered 1PPS, standard operation however doesn't preserve phase at the output.
On datasheet there's a reference about zero-delay mode, however the way it obtain it is not completely clear to me.
From what I understand this mode uses the 1PPS input rising edges to clear the divisor of OUTPUT7, thus synchronizing rising edges of output to those of input.
But what about input jitter and phase errors introduced in this way?
I mean, if the output frequency is 10MHz, jitter on input could easily reset the divisor one cycle early / late, causing bad frequency generation... or not?
Please add some digression about this, a give your valuable advice.
Thanks
Andrea
