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LMK00804B-Q1: Clipped sine-wave input from TCXO

Part Number: LMK00804B-Q1

Good day.

Is it possible for one of the inputs of the LMK00804B-Q1 to accept a clipped sine-wave clock signal from a source such as a TCXO device?

What would be the best input and configuration to use when the datasheet for the TCXO recommends that its output be AC coupled using a capacitor to the load, in this case the input to the LMK00804B-Q1?

The level of the clock signal is typically 1.0 Vp-p, with a minimum level of 0.8 Vp-p

Thank you for your support.

Marco

  • Hi Marco,

    You will want to use the differential input CLK_P/N due to the input swing. One way to do it is AC-couple the TCXO to CLK_N, and bias CLK_P to VDD/2 using a resistor divider

    Kind regards,
    Lane

  • Hello Lane, good afternoon.

    Thank you for your response and guidance. I appreciate it.

    The information and clock input configuration that you provided is very useful.

    I suspected that I needed to use the CLK_N input because it is internally biased to VDD/2 with a pull-up and a pull-down, but was not sure what to do with CLK_P. That means CLK_P will also be biased to VDD/2 with the external resistor but I do not need to connect any other signal to it; correct?

    Will the output from the LMK00804B-Q1 be shifted 180 degrees with respect to the input because of using the CLK_N port?
    In my application that should not be a problem because all parts using that clock output will see the same version of the clock signal.

    Best Regards,
    Marco

  • Hi Marco,

    Correct, you would not need to connect another signal to the CLK_P input

    Correct again, the clock output will be phase shifted when using only the inverting input. However a similar approach could be taken using the CLK_P input instead to avoid the 180 degree phase shift

    Kind regards,
    Lane