Hi all
In my design i am using two CDCM6208V1HRGZR in sequence.
Both are powered from single 3V3 Supply with ramp up of about 5ms and starting at the same time.
First input of CDCM6208 is driven by Oscillator and the output of first CDCM is used as input for the second CDCM.
That means that second CDCM is powered but sees a valid clock input about 15ms after powerup.
Is that working properly or is the second going into timeout when it sees no valid clock for the first 15ms ?
There are some timeout counters built in. Will that work when for first 15ms there is no valid clock?
One other idea would be to use the PDN pin with a 1uF capacitor to delay the second CDCM, but would that slow rising edge violate the input requirements for the CDCM6208.
In the datasheet there is a specification for PDN input for deltaV/deltaT of minimum 0.75V/ns. What does that mean? The 1uF capacitor gives a slow ramp on PDN of about 15ms. Is that rising too slow?
Thanks verry much
BR,
Gregor
