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CDCM6208: Input Clock start delay

Part Number: CDCM6208

Hi all

In my design i am using two CDCM6208V1HRGZR in sequence.

Both are powered from single 3V3 Supply with ramp up of about 5ms and starting at the same time.

First input of CDCM6208 is driven by Oscillator and the output of first CDCM is used as input for the second CDCM.

That means that second CDCM is powered but sees a valid clock input about 15ms after powerup.

Is that working properly or is the second going into timeout when it sees no valid clock for the first 15ms ?

There are some timeout counters built in. Will that work when for first 15ms there is no valid clock?

One other idea would be to use the PDN pin with a 1uF capacitor to delay the second CDCM, but would that slow rising edge violate the input requirements for the CDCM6208.

In the datasheet there is a specification for PDN input for deltaV/deltaT of minimum 0.75V/ns. What does that mean? The 1uF capacitor gives a slow ramp on PDN of about 15ms. Is that rising too slow?

Thanks verry much

BR,

Gregor

  • Hi Gregor,

    Please read datasheet 10.1.3 for explanation. PDN pin can be delayed with no problem.

    Regards,
    Hao

  • Hi Hao

    Thanks for reply

    PDN delay is ok and solved.

    I try to avoid the PDN delay as it needs big capacitor and there is no time for a redesign of the product. 

    For 2nd question. When the CDCM is powered up and the input clock is starting 15ms after the powerup, then according to Datasheet the CDCM is waiting until clock is stable. The question was: is there a timeout or will CDCM6208 wait even for such long missing Clock as is in our desing for around 15ms? Will it work and lock reliably? We will use several 10'000 pcs of this clock driver and need to be 100% shure that al products are working reliably.

    BR,

    Gregor

  • Hi Gregor,

    As far as I'm concerned, there is no timeout and the VCO will start calibration whenever the reference becomes valid.

    Regards,
    Hao

  • Thanks verry much