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LMH1983: User Defined Format Mode

William Slattery1
Prodigy 30 points
Part Number: LMH1983

The LMH1983 accepts standard video time signals in order to derive locked audio and video clocks. It also has the option to accept fixed 10MHz and 27MHz clocks and locks its internal PLLs to those. In addition, it has the option for User Defined Formats where custom reference signal parameters are specified.

I am trying to use the part in User Defined Format mode to lock to an18.5625MHz clock via the HIN input. This frequency is available from an FPGA based SDI receiver that does not have a reliable HSYNC output. This frequency is 148.5MHz / 8 and is 27MHz x 11/16.

Some questions ...

1) Is this user defined situation possible?

2) What is the maximum frequency that can be input via the HIM pin and into the R divider?

3) What is the optimal phase detector frequency is this case? I am currently using R=1100, N=1600 which provides 16.875kHz PD frequency.

4) How should User Auto Format low and high range registers be set in this case?

5) How should User Auto Format Lines per Frame be set in this case?

6) What User Auto Format Charge Pump Setting Should be used?

7) How should User Auto Format Miscellaneous settings be set?

8) Once configured correctly should I expect the PLL1 lock status in register 0x2 to be set.

  • 0
    TI__Genius 16845 points

    A1) Yes, it is possible. 

    A2) There is a 10 bit R-divider and the maximum allowed phase detector frequency is around 67kHz, which would correspond to a maximum input frequency of approximately1023*67kHz or ~68MHz. You will not have issues with 18.5625MHz input.

    A3) R=1100 is not possible with a 10-bit R-divider ; maximum value is 1023. It is also important to note that the PFD range is about 6-67kHz.

    Based on your input frequency and 27MHz VCXO, R = 286 and N = 416 are the minimum possible values where you operate near the max PFD.

    The phase detector frequency will impact the bandwidth setting for your loop filter, as detailed in equation 2 on datasheet page 14. 

    A4) Set the high and low to as the number of 27MHz clocks that occur in 20 Hsync periods. For example, let's assume your 18.5625MHz H input looks like a square wave. Then in 20 input cycles, we get 20*11/16 = 13.75 pulses. In this case, you might set the low value to 13 and the high value to 14.

    A5) The 13-bit LPF value sets the TOF1 frequency. You will notice in Table 2 that the Total Lines per frame counter is equal to the PD periods per frame counter

    A6) You will want to configure the charge pump current based on the design considerations outlined in datasheet section 8.3.2. As detailed, charge pump current impacts the loop bandwidth.

    A7) You may want to enable EN_USERMODE to use your user defined mode rather than auto format detect. Interlaced/progressive refers to HD video like 1080i or 1080p, it may not apply to your signaling.
    USR_IN_VS_CODE is used to set the values of TOF2_RST and TOF3_RST using a lookup table. If you do not need to TOF2 or TOF3, set USR_IN_VS_CODE = 0b1000

    A8) Yes, that is correct

    Kind regards,
    Lane