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LMK04616: LMK04616

Moti Cohen
Prodigy 170 points
Part Number: LMK04616

Hi

As I know, temperature change the delay between ClkinX to ClkoutX.

Question: If I am using two devices, Is it true to say that as the temperature change (same In both devices), the delay from ClkinX to ClkoutX change and move at the same direction?

Thanks

Moti

DSIT

  • 0
    TI__Mastermind 28550 points

    Hello Moti,

    Yes, this is generally true.  Only when including PLL1 may the phase not follow well.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 170 points

    Hello Timothy

    Thanks for your very quick replay.

    The word that bothers me in your answer is "general".

    What is the biggest difference in delay between two devices at the same temperature?

    Does TI have an spec on this subject? I mean if TI has a commitment that the delay shift in temperature will always be in the same direction?

    Thanks

    Moti

  • 0 in reply to Moti Cohen
    TI__Mastermind 28550 points

    Hello Moti,

    I say "general" because we don't have a specific specification on the biggest difference between two devices at the same temperature.  However we do have some data, as illustrated in the e2e post, https://e2e.ti.com/support/clock-and-timing/f/clock-timing-forum/987282/lmk04616-datasheet-parameters-confuse

    Please note that this is in buffer mode.

    For which mode or modes are you interested to know the propagation delay?

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 170 points

    Hi Timothy

    I am using only PLL2 with zero dealy mode when the reference clock inserted to OSCin.

    As I understand my mode is called ZDM.

    If this is true I am confused. The information written in the link you added explain that the skew between devices in any temperature range is about 30pS at ZDM, and about 700pS at buffer mode. The first graph shows skew for ZDM. At this graph I can see that the skew is ~500 and it is ZDM not buffer mode. I expected to 30pS at this mode.

    Maybe I do not understand what "buffer mode" is. Can you help?

    Thanks

    Moti

    DSIT

  • 0 in reply to Moti Cohen
    TI__Mastermind 28550 points

    Hello Moti,

    Buffer mode is where an input clock at CLKin can be directly routed to CLKout bypassing both PLLs.

    Let me review this info and get back with you.

    73,
    Timothy

  • 0 in reply to Moti Cohen
    Prodigy 170 points

    Hi Timothy

    I hope you are checking the skew issue between two devices in buffer mode and in ZDM mode.
    I am waiting to your replay.

    Thank you for your help
    Moti
    DSIT
  • 0 in reply to Moti Cohen
    TI__Mastermind 28550 points

    Hello Moti,

    Sorry for the delay.

    Yes, so I reviewed the other post.  It suggests that using ZDM mode does have more consistent propagation delay variation than does the mode where the inputs are directly buffered to the output.

    Therefore, to minimize part-to-part variation, I suggest using PLL2 ZDM mode... however I don't have a worst case spec.  But given that different process corners were use in this data and it is still very close, for devices at the same temperature, it would be reasonable to expect less than 30 ps error device to device for devices at the same temperature.  If they are different temperatures - you would have to account for that variation also.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 170 points

    Hi Timothy

    As I understand:

    1. At ZDM mode, the skew between devices at the same temperature will be ~30pS. 

    2. TI does not commit to maximum skew.

    I wonder, the device spec shows that the skew between output clocks at the same component is 60P (typical). Is it likely that the difference between components will be only 30P?

    Thanks for your replay

    Moti

    DSIT

  • 0 in reply to Moti Cohen
    TI__Mastermind 28550 points

    Hello Moti,

    Good point about the skew between output clocks.  The above data is for only one output clock (CLKout0) and focuses on input to output propagation delay variation.  On top of this I would add the output to output skew.

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 170 points

    Hi Timothy

    How can I design a circuit with two components running in parallel if there is no spec from TI regarding the skew between the units?
    Is there a number that TI can commit to?

    Thanks

    Moti

    DSIT