DAC38RF89EVM: EVM connection fails

Hi Itoh-san,

The DAC38RF89 EVM GUI is located in the following:

https://www.ti.com/lit/zip/slac722

When you press the "reconnect" button on the GUI, please advise what happens

Please also ask the customer to check the Hardware Manager to see "USB Serial Converter" show up in the PC. Thank you

Hi Kang-san,

Thank you so much for your support. Now the EVM is successfully connected.

However, my customer has another problem.

My customer set up the GUI and generate tone, and then pressed  "Send" but it doesn't correctly work.

It shows "Configure DAC DATA_READ_FAILED ... ".

The device is selected by HSDC Pro v5.20 DAC pane, and the firmware is loaded.

It is stuck on the DAC38RF8x EVM user guide page 11 section 8. 

Could you please help me to address this?

To check the configuration, please find below link for some GUI screen shots.  (Please access from TI internal network or VPN)

https://tidrive.itg.ti.com/a/BtzPthlcz_IU3M-m/87771448-8f46-40dd-8426-8dac69275223?l

Regards,

Itoh 

Itoh-san,

What version of TSW14J56EVM are they using? The firmware file that was downloaded does not appear to be correct. They should be using a Rev D version of this board.

Have the customer verify the DAC PLL is locked. Also make sure the 5V supply to the TSW4J56EVM can provide 4A of current.

Regards,

Jim

Hi Jim-san,

My customer is using Rev B board. Does my customer need to purchase new TSW14J56EVM?

Also, could you please let me know how to verify if the DAC PLL is locked?

Also, I have one additional question.

This DAC can adjust the +3dBm fs output level by Gain for path AB Register (0x32 and 0x33).

When the input signal is full scale and Gain for path AB register is swept, could you please let me know the minimum and maximum output level (dBm) and step level? 

Best regards,

Itoh

Itoh-san,

The software team has confirmed this EVM should work with HSDC Pro GUI v5p2. 

See attached document for verifying the status of the DAC PLL.

The gain for AB register 0x32 is a direct multiplication of the digital data received by this function. The multiplication factor range is from 0 to 2.  If you have 300mV coming in to this block and the gain is set to 1.25, the output will be 375mV. The GUI default value is a gain of 1. Care must be taken when using this function as you can saturate the output if the input is high and you use a setting above 1. The multiplication factor is 0.001 per bit of this register setting. 

Regards,

Jim  

Document I forgot to attach.

DAC38RF89_real_821_PLL.pptx

Hi Jim-san,

Thank you so much.

Please allow me to ask you detail about the gain and output level.

1. When the output is 375mV, it will be +4.5dBm if the impedance is 50Ohm.

The datasheet full scale output power is 3dBm.

So, do you mean it can output larger than 3dBm?

Please kindly let me the recommended output range to avoid the saturation.

2. When the input to DAC block is 300mV, the output will be 300mV (2.55dBm) at gain=1V/V, 

and the output can be adjusted from 300uV (-57.45dBm) at gain=0.001V/V

to 600mV (8.57dBm) at gain=2V/V, correct? 

One more important question, do you mean the software team has confirmed this EVM should work with HSDC Pro GUI v5p2 in Rev B board? 

I still wonder if the customer needs to prepare Rev. D board or they can keep going with Rev. B board. 

Best regards,

Itoh 

Itoh-san,

Would you be able to order the latest TSW14J56 EVM for the customer? The latest in the E-store should be revision E of the TSW14J56 and is known to be stable with the DAC38RF89 EVM. Thank you.

FYI, Jim is on vacation and will return on 10/10. Thank you.

Hi Kang-san,

Now my customer is testing with Rev. E board, but the problem is still there. Could you please check?

Please find attached. The zip file includes multiple GUI screenshots and note which explains how it was captured.

DAC38RF89EVM.zip 

Regards,

Itoh

Itoh,

The customer must get the DAC PLL to lock before trying to get an output. Make sure they are sending a 625MHz clock with at least 12dB of power to SMA J4 and the shunt on JP10 is removed. The clock must be present before configuring the DAC. After doing a reset, load defaults and programming the DAC, click on PLL Auto Tune. Verify that the PLL LF Voltage is between 3-5. This must be meet before moving on. The TSW14J56EVM is not required to perform this test.

Regards,

Jim

Hi Jim-san,

Thank you for your suggestion. Some questions I posted above has been somehow left, so please allow me to post it again.

1. When the output is 375mV, it will be +4.5dBm if the impedance is 50Ohm.

The datasheet full scale output power is 3dBm.

So, do you mean it can output larger than 3dBm?

Please kindly let me the recommended output range to avoid the saturation.

2. When the input to DAC block is 300mV, the output will be 300mV (2.55dBm) at gain=1V/V, 

and the output can be adjusted from 300uV (-57.45dBm) at gain=0.001V/V

to 600mV (8.57dBm) at gain=2V/V, correct? 

 Regards,

Itoh

Hi Jim-san,

About the EVM connection, the test with DAC EVM only looks working correctly. However, when connected to TSW54J56EVM, it failed again.

Could you please support?

Please find attached GUI screenshots.

DAC_20211014_1459.zip

◆DAC EVM only test.

5V was powered to DAC EVM.
JP10 was removed.
625MHz 12dB clock was provided to SMA J4 from the signal generator.
The test has been done with only DAC EVM.
DAC GUI was launched, and then the parameter configuration was done following the slide (reset, default load, DAC TEST).
Clicked "Configure DAC" and "PLL Auto Tune".
Switched to DAC clock display and validated that PLL LF voltage was 5V.

With the single DAC EVM test, the result was confirmed as instructed.
(Attachment: gamen-20211014-1445-01.png)

◆DAC EVM + TSW14J56EVM (Failed)

After that, TSW14J56EVM was connected and test has been done following the DAC TEST slide.
The error happened as reported before and the test was failed.

（　Attachment：　gamen-20211014-1449-02.png　）

Launching the HSDC pro and selected DAC38RF8X_LMF821, then tried to download the firmware.
The error happened as attached
（　Attachment：　gamen-20211014-1449-03.png　）

The GUI display after setting parameter, clicking "Create Tones"
（　Attachment：　gamen-20211014-1449-04.png　）

Clicking the "Send" button, then error happened
（　Attachment：　gamen-20211014-1449-05.png　）

Regards,

Itoh

Hi Jim-san,

Thank you for so much for checking the GUI problem and the question#1.

Could you please check question #2 as well? (This question is just a confirmation)

2. When the input to DAC block is 300mV, the output will be 300mV (2.55dBm) at gain=1V/V, 

and the output can be adjusted from 300uV (-57.45dBm) at gain=0.001V/V

to 600mV (8.57dBm) at gain=2V/V, correct? 

Regards,

Itoh

Itoh,

The Gain AB block has a gain from 0 to 2. This block uses a 12 bit address. So the gain value is 0.000488/bit. If you have 300mV coming in and using the lowest gain setting, the output will be 300mV * 0.000488 = 146.4uV. 

If you use the largest gain setting, the output will be 2 * 300mV = 600mV.

Regards,

Jim

Hi Jim-san,

Your answer is different from what you've provided 20 days ago. But OK, I understand, thank you.

>The multiplication factor is 0.001 per bit of this register setting. 

Regards,

Itoh

Hi Jim-san,

Thank you, I understand.

Sorry for bothering you again, but could you please let me know how to derive the DAC input (300mV in your example) from the RX input?
Both RX input and DAC input should be digital value, so I my customer is wondering how to practically calculate the value.

Regards,

Itoh

Thank you so much! The problem is resolved. It was due to the power supply limitation as you pointed out.

Regards,

Itoh