ADS1258: Interference from channel 0 and channel 7

Hi Giovanni,

Can you explain to me how you are reading data back from the ADS1258? Are you using auto-scan or fixed-channel mode, what data rate, any delay time, pulse convert vs continuous convert, etc.?

Also, how are you determining that there is noise on the load cell channel? Are you reading back the load cell channel while adjusting the pot, and then you see some unstable counts? If yes, does the noise occur only when the pot is being adjusted i.e. if the pot is stable at any random point from 0 to FS, do you still see noise?

-Bryan

i Bryan, my firmware designer send me this configuration about ADC:

ADS1258_REG_CONFIG0 = ADS1258_SPIRST_256 | ADS1258_MUXMOD_AUTO | ADS1258_BYPAS_INT | ADS1258_CLKENB_ENB | ADS1258_CHOP_DIS | ADS1258_STAT_ENB

ADS1258_REG_CONFIG1 = ADS1258_IDLMOD_STANDBY | ADS1258_DLY_16US | ADS1258_SBCS_OFF | ADS1258_DRATE_23739SPS

About noise on load cell, the original digital value is divided by 128. when potentiometer is at 0 scale tha analog value of load cell is about -2, when potentiometer is at full scale, le digital value of load cell goes to -7

Hi Giovanni,

Thanks for the additional information. I am still a bit unclear how you are determining the noise on the load cell - can you please walk me through the procedure step by step for determining the noise when the pot is enabled, including:

• Are you scanning through all of the channels even though only Ch0 and Ch7 have sensors attached? Or are you just reading Ch0, then Ch7, then Ch0, then Ch7, and so on?
• Are you using the START pin or command?
• Pulse convert or continuous conversion mode?
• How are you reading back data? Are you looking for the DRDY signal, or just trying to time conversions?
• Are you using the RDATA command or read data direct mode?
• How is the noise determined? Are you performing statistical analysis on multiple ADC measurements? If so, how many?
• Can you tell me what the numbers "-2" and "-7" correspond to? How do these relate to the actual ADC codes you are getting from the device?

If you have logic analyzer data for the entire loop through all channels, that might be useful as well.

-Bryan

Hi Bryan, all channels are read continuously.

Start pin is used.

Continuous mode.

DRDY pin used.

Command mode

Each channel is sample at 2Kz. Digital value (signed value) of ADC is divided by 128. There is a low pass filter on this value, and then are stored at 50Hz on a excel file. making a graph using this value you can see the changing of CH0 while CH7 change.

We haven't logic analyzer

Hi Giovanni,

Can you send me the raw ADC codes (in hex) that you receive from the ADC? So basically whatever data you received from the ADC to make the plots in your last post, without any scaling or filtering?

Also, what is the expected load cell value on Ch0? You said it varies from -2 to -7, but what value(s) should you be getting?

Have you tried increasing the delay time (ADS1258_DLY_16US) and seeing if that helps?

-Bryan

Hi Bryan,

i need some day to collect adc data you ask me.

about the delay time (ADS1258_DLY_16US) we can't increase it.

Sounds good Giovanni, please let me know.

For the delay, I ask that you just perform this test to see if it makes a difference in the results. I would not expect you to keep this delay in your final system, but it might help us understand what is going on

-Bryan

Hi Bryan, i have collect some acquisition on an excel files.

I understand that it seem that a channel can disturb only the next channel (CH1->CH2.... CH8->CH1).test.xlsx

Hi Brian, I made some measurements on analog stage (see picture for reference). I note that when the problem appears, the differential voltage on CH0 change ( on C48, ie direct input pin of ADC). But the differential voltange from Instrumentational Amplifier doesn't change (Vo_pin1 - Vo_pin7). it's seem that C48 in charged a little from the ADC, falsing next measurement on this channel. Can this be true ?? No i try to remove C48 from adc input.

Hi Giovanni,

Yes, this could be it. Have you simulated this circuit in SPICE to see the transient response?

I quickly put this into TI-SPICE using our OPA188, which is a similar amp to the ADA4522. See the schematic and transient response below. Specifically, the time it takes for the data to be settled given an input step of only 10mV. Per the diagram, it takes approximately 3.6ms for the data to settle. However, the ADC modulator is sampling at tSAMPLE = 2 / fCLK = 0.127us, and the conversion period is 1 / 23.7k = 42us. I would encourage you to rethink your signal conditioning circuit design. You can use simulation tools to determine if the circuit will settle during the conversion period.

Hi Bryan, i try to remove the capacitor across An+/An- and the problems disappears. But i don't understand why with a 100nF (original value) i have a variations of about 5 point (adc value/128), and with a 10nF the variations is of 15 points !! with 47nF and 4.7nF the risult is same as 100nF. With 1nF the problem disappears. Do you think this capacitor can be removed without problems in conversion stability ??

thanks a lot for your time.