• State TI Thinks Resolved
  • Locked Locked
  • Replies 15 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 3807 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Starterware/TSW30SH84EVM: TSW30SH84EVM with TSW1400 test file issue

Joshua Johnson55
Intellectual 385 points

Part Number: TSW30SH84EVM

Tool/software: Starterware

Hello,

I am trying to run the Texas Instrument test file single tone complex test file with my setup which is a TSW30SH84EVM and TSW1400 and I am not getting any signal coming out. I really don't understand what I am doing wrong because I am able to run all of the WCDMA test files, I believe it has something to do with two column data that I'm missing in the settings of the TSW30SH84EVM or the TSW1400. Any help would be greatly appreciated. Attached  is the TI test file path I'm talking about:

"C:\High Speed Data Converter Pro\Test Files\single_tone_cmplx_32768_250MSPS__BW_25.1MHZ.csv"

Thanks,

Joshua Johnson

  • 0
    Intellectual 385 points
    I think it has to do with the clock settings on the TSW30SH84 software because its default is 2 x 737.28Msps could I please get help with setting the clock for 2 x 250Msps and 2 x 1.2Gsps
  • 0 in reply to Joshua Johnson55
    Intellectual 385 points
    Could I please get some help with this I would really appreciate it.
  • 0 in reply to Joshua Johnson55
    Intellectual 385 points
    Could I at least get an explanation as to the relation's on the LMK4800 control that governs the msps on the TSW30SH84. I've seen in another post a TI employee provided clock settings for 2x614.34 but I don't understand the correlation in the changing of values on the LMK4800 settings.
  • 0 in reply to Joshua Johnson55
    TI__Genius 12780 points

    Hi Joshua,

    Please take a look at the power point. I was able to get the file to output ok.

    TSW30SH84_SingleTone.pptx

    The thing that governs the data rate (MSPS) at HSDC Pro is the frequency you supply to the DAC (DAC_CLK) at J12, and the interpolation rate you are using. If you use a 1 GHz clock and have 4x interpolation, you data clock (coming from HSDC Pro and the TSW1400) will be 1GHz/4 = 250 MSPS.

    Let me know if this procedure worked for you.

    Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 385 points
    Okay this is great thank you so much, but isn't there a way to change the data rate through the settings on the TSW30SH84 GUI also? Like maybe through the LMK4800 settings?
  • 0 in reply to Joshua Johnson55
    TI__Genius 12780 points
    Hi Joshua,

    To answer your question, yes, you can change the data rate using the LMK4800 dividers in the GUI, but it is a second order effect of changing the DAC Clock. You must account for interpolation to derive the Data Clock. (You can also change the data rate using different interpolation rates as explained below)

    The DAC clock is the clock frequency that you supply to the EVM at J12 (CLKIN1). This clock signal goes to the LMK, and can be divided down, but in the example I provided, the divider is set to 1, so the DAC clock is effectively passed straight through from the input (J12) to the DAC IC. If you wish, you can divide this frequency using the LMK, but keep in mind that this is directly changing the DAC Clock. The Data Clock will change proportionately with the DAC Clock, but remember that the Data Clock is equal to the DAC Clock divided by interpolation.

    For example, you provide a 1 GHz DAC Clock signal to the EVM. You then set the LMK to divide the DAC Clock by 4, and use 2x interpolation. Your DAC Clock now becomes 250 MHz (1GHz/4), and your Data Clock is 125 MSPS (DAC Clock/ Interpolation = 250 MHz/2).

    Hope that helps.

    Regards,

    Dan
  • 0 in reply to dBrock
    Intellectual 385 points
    Hi Dan,

    Thank you for this information this is really useful, but Im still having issues lowering the data rate on the TSW30SH84 EVM below 1228.56 (2 x 614.4Msps). Could you maybe send me a tutorial or a file similar as to how you showed me to change the clock externally but through the software gui of the TSW30SH84 EVM without the external clock? This would be so helpful because I could learn how to set it to other data rates without using the external clock. If you could do this for 2 x 250 msps I would be so grateful.

    I really appreciate all of your help,
    Joshua Johnson
  • 0 in reply to Joshua Johnson55
    TI__Genius 12780 points
    Hi Joshua,

    Are you planning on using the PLL to provide the DAC/Data clocks? By 2 x 250 msps, do you mean 2x interpolation and a resulting data rate of 250 msps? I will start working on this, but it may be a few days before I can get it to you.

    Regards,

    Dan
  • 0 in reply to dBrock
    Intellectual 385 points
    Hey Dan,

    We haven't used the PLL in the past but I'm not opposed, maybe if it's not too much you could show me one with PLL and one without. But yes by 2x I mean interpolation so a resulting data rate of 250 msps. Thank you so much Dan this will be very helpful for us.

    Joshua Johnson
  • 0 in reply to Joshua Johnson55
    TI__Genius 12780 points

    Hi Joshua,

    Take a look at this powerpoint (seems pretty familiar at first). I took care to ensure the reference clock doesn't change (only GUI and HSDC Pro).

    TSW30SH84_AdjustingDataRateWithGUI.pptx

    I am working on the PLL version, and will have that posted soon.

    Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 385 points
    Hey Dan,

    This is so great thank you very much this is really helpful, what I meant by without the use of external reference is lowering the data rate as you have but without any use of J12 on the TSW30SH84EVM. So to clarify I am asking how to lower the data rate to 250 MSPS without the use of J12 but solely through the TSW30SH84EVM GUI, a signal to J19, and the HSDC Pro. Im sorry for the misunderstanding but we really would like to lower the data rate without the use of the external clock at J19.

    Thanks,
    Joshua Johnson
  • 0 in reply to Joshua Johnson55
    TI__Genius 12780 points

    Hi Joshua,

    I'm sorry for the misunderstanding! Looking at the TSW30SH84EVM user's guide, this kind of operation is not possible using only the LMK. Please read the note in the upper right hand corner of the image below. I am checking to see if Single PLL mode will work while utilizing an on-board crystal oscillator (jumper modification). This information is located in the Optional Configuration Section of the user's guide.

    The signal that goes to J19 is for the TRF3705 RF modulator, and basically "mixes" the output from the DAC with the frequency from J19. The TRF is independent of the DAC, so this signal has no influence on the data rate between the TSW1400 and the DAC. If you look at the power point I made, this explains why the spectrum analyzer shows the DAC output (30 MHz signal generated from data sent by the TSW1400) with an offset of 1780 MHz (frequency of signal at J19).

    I will need to verify in the lab, but I believe you can use just the external reference for the DAC (J12) and not the TRF LO signal (J19). However, if this is how you intend to use the device, I would suggest proceeding with the DAC34SH84EVM since it doesn't have the TRF3705 section. Do you currently have the TSW30SH84EVM in your possession?

    Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 385 points
    Dan,

    Yes I have the TSW30SH84EVM and I'm aware that J19 is intended for sending a signal to be mixed Im sorry for not clarifying. So you're saying it is not possible to reduce the data rate of the DAC through the use of just the LMK divider? Also could you still send me the powerpoint you were going to make for the PLL version? I find your power points very helpful!

    Thanks,
    Joshua Johnson
  • 0 in reply to Joshua Johnson55
    TI__Genius 12780 points

    Hi Joshua,

    You can reduce the DAC rate(clock) with the LMK which will change the data rate (data rate = DAC rate/interpolation).

    Please see the attached power point for using PLL2. Note that this PLL resides inside of the LMK (not the PLL on the DAC die).

    TSW30SH84_PLL2.pptx

    Let me know how this works for you.

    Regards,

    Dan

  • 0 in reply to dBrock
    Intellectual 385 points
    Hi Daniel,

    Yes this is exactly how I've been using the TSW30SH84EVM, could show me how you would reduce the DAC clock to (2 x 250 msps) through this way? This would be the answer I've been looking for the entire time. Thank you so much.

    Joshua Johnson