SN75DP159: SN75DP159

Roi

1. Why do you need the 100ohm termination between HDMI_D[n]p_A and HDMI_D[n]n_A? Is the source a DC-coupled or AC-coupled HDMI?

2. Are you bypassing the DP159 DDC and use the external DDC? When not use the DP159 DDC, please pull SCL_SRC and SDA_SRC to ground

3. Is this HDMI1.4 or 2.0? Can you measure the TDP159 clock output and are you able to see a valid clock frequency?

Thanks
David

1. The source is the FPGA

2. I pulled SCL_SRC and SDA_SRC to ground - still not working.

3. HDMI 2.0

Roi

Roi

Are you bypassing the DP159 DDC and use the external DDC?

For HDMI2.0, can you please read out the DP159 registers? We want to make sure the TMDS_CLOCK_RATIO_STATUS bit is set to 1. We also need to measure the clock output frequency is equal to HDMI2.0 data rate / 4. 

Can you toggle HPD_SNK and see if you can get video out?

Thanks

David

Hello David

Bellow is the register read:

const struct Reg_init_HDMI_tbl{

   unsigned char Reg_Addr;

   unsigned char Reg_Val;

   unsigned char Reg_Mask;

} Reg_init_HDMI[] = {

  {0x09, 0x06, 0xCF},

  {0x0A, 0xF6, 0xFF},

  {0x0B, 0x1A, 0xFB},

  {0x0C, 0x48, 0xFF},

  {0x0D, 0x01, 0xFF},

  {0x0E, 0x0F, 0x0F},

  {0x10, 0x81, 0xBF},

  {0x11, 0xAA, 0xFF},

  {0x12, 0x55, 0xFF},

  {0x13, 0x0A, 0x0F},

  {0x14, 0x00, 0x0F},

  {0x15, 0x00, 0x07},

  {0x16, 0x00, 0xF7},

  {0x20, 0x0A, 0x0F}

};

We also need to measure the clock output frequency is equal to HDMI2.0 data rate / 4. - I will measure it tomorrow.

we want to make sure the TMDS_CLOCK_RATIO_STATUS bit is set to 1 - we change it to '1' and no video.

Are you bypassing the DP159 DDC and use the external DDC? - I don't understand your meaning.

Roi

Roi

How do I read the Reg_init_HDMI[], first column is the register address, second column is the data, and third column is mask? 

You can manually set TMDS_CLOCK_RATIO_STATUS bit, but this bit should be set automatically based on the DP159 snooping of the DDC bus between the source and the sink. 

The DP159 uses clock stretching for DDC transactions. As there are sources and sinks that do no perform this function correctly a system may not work correctly as DDC transactions are incorrectly transmitted/received. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The DP159 will need its SDA_SNK and SCL_SNK pins connected to this link in order to the SNx5DP159 to configure the TMDS_CLOCK_RATIO_STATUS bit. Care must be taken when this configuration is being implemented as the voltage levels for DDC between the source and sink may be different, 3.3 V vs 5 V. SDA_SRC and SCL_SRC need to be tied to ground in the snooping configuration.

Thanks

David 

Hello

Here is how we configure the retimer please tell us what we do wrong, first column is the register address, second column is the data, and third column is mask.

Also, can we see visuals on the monitor by configuring the test pattern?

 const struct Reg_init_HDMI_tbl{

   unsigned char Reg_Addr;

   unsigned char Reg_Val;

   unsigned char Reg_Mask;

} Reg_init_HDMI[] = {

  {0x09, 0x06, 0xCF},

  {0x0A, 0x76, 0xFF},

  {0x0B, 0x1B, 0xFB},

  {0x0C, 0x00, 0xFF},

  {0x0D, 0x00, 0xFF},

  {0x0E, 0x00, 0x0F},

  {0x10, 0x00, 0xBF},

  {0x11, 0xAA, 0xFF},

  {0x12, 0x55, 0xFF},

  {0x13, 0x0A, 0x0F},

  {0x14, 0x00, 0x0F},

  {0x15, 0x00, 0x07},

  {0x16, 0x00, 0xF7},

  {0x20, 0x0A, 0x0F},

  {0x0A, 0x04, 0x04} // Apply changes

};

Hi,

It looks the DP159 is being programmed so the HPD_SNK is not being passed onto the HPD_SRC, does the FPGA expect to see HPD_SRC high?

If you don't force the TMDS_CLK_RATIO_STATUS to a 1, do you see the TMDS_CLK_RATIO_STATUS being automatically set to 1?

What is the clock output frequency?

Thanks

David

Hello David

We are Not using the HPD on the FPGA
The TMDS_CLK_RATIO we will check to make sure it is 1
The FPGA should output 148.5 which is 1/40

Hi,

How does the FPGA know a sink has been connected?

Besides checking the FPGA output, please also check the DP159 clock output and make sure it is 148.5MHz as well.

Thanks

David

Hello

We ignore the FPGA sink since data is provided constantly from a FPGA.

Roi

Roi

You need to make sure the FPGA turns off its output and only enables the output after the TMDS_CLK_RATIO_STATUS bit has been set to 1 for HDMI2.0.

Thanks

David 

Hello

9.2 Fuctional Block Diagram - what is the fuctionality of  the active DDC Block?

Roi

Roi

The active DDC block is an active DDC repeater, so it acts as a secondary to the source DDC primary and a primary to the sink DDC secondary if DDC is routed through the DP159. It does several functions. 

1. Level shifting between 3.3V and 5V

2. Set/Clear TMDS_CLK_RATIO_STATUS depends on the DDC communication between the source and the sink.

3. Implementing clock stretching on the SDA_SRC and SCL_SRC. Please note that not all sources support clock stretching. In this case, you need to implement the DP159 DDC snooping option.

Thanks

David 

Thanks for your quick respond.

Do we need to write to the monitor by the ISC and changing register to operate it?

If yes, which register we need to write/read?

Regarding the snoop, 9.4.3 DDC Training for HDMI2.0 Data Rate Monito is the only description?  (:"the source will write to slave address 0xA8 offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS. The SNx5DP159 snoops this write to determine the TMDS clock ratio and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a 1 is written, then the TMDS clock is 1/40 of TMDS bit period. If a 0 is written, then the TMDS clock is 1/10 of TMDS bit period. The SNx5DP159 will always default to 1/10 of TMDS bit period unless a 1 is written to address 0xA8 offset 0x20 bit 1. ")

Roi

Roi

The FPGA (source) needs to first verify the monitor has a valid HF-VSDB in the E-EDID in which the SCDC_PRESENT bit = 1.

If the SCDC_PRESENT bit is 0, the FPGA should not access the monitor SCDC register.

If the SCDC_PRESENT bit is 1, then FPGA access the monitor SCDC register by writing to slave address 0xA8 offset 0x20 bit1, TMDS_CLOCK_RATIO_STATUS for HDMI2.0. You will also need to write to offset 0x20 bit 0 to enable scrambling for HDMI2.0. Please note for 7-bit I2C address, 0xA8 is 0x52.

Please also note that the FPGA needs to turns off its output first, write to the MDS_CLOCK_RATIO_STATUS bit, wait for min of 1m and max of 100ms, and then turn on its output. 

Thanks

David

Hello David

Sorry for my late respond, I was in vacation.

Please also note that the FPGA needs to turns off its output first, write to the MDS_CLOCK_RATIO_STATUS bit, wait for min of 1m and max of 100ms, and then turn on its output. - first we configure the register by the MCU and after it we configure the FPGA.

1. We read '0' at addr 15h,bit 7 DESKEW_CMPLT. what can be the problem.

2. Register 1A, the value is different from '0'

3. Register 0F, PV_TIP[3:0] - Patternt is no locked

4. There is a test pattern from the retimer to the monitor?

Roi

Roi

The DP159 has a deskew circuit to compensate for input inter-pair skew. From the FPGA, how many consecutive special symbol in the TMDS stream are you sending?

Register 0x1A is the Bert count and it is a test mode only. 

Did you get a chance to measure the DP159 clock output frequency?

Thanks
David

Hello David

1. I don't have a clock output from the retimer.

2. How can I operate the test pattern of the retimer?

Roi

Roi

If you do not see a clock output from the retimer. 

1. Please make sure HPD_SNK is high
2. Please make sure you have 50ohm to 3.3V termination on the clock output

For test pattern generation, please see this app note, https://www.ti.com/lit/ug/sllu294/sllu294.pdf. But why do you care about the test pattern generation? You don't need test pattern to get HDMI2.0 working. Are you able to get HDMI1.4 to work?

Thanks
David 

Hello Davis

Should I connect 50ohm to 3.3V termination on the data output too?

Roi

Roi

Most HDMI receiver already has internal 50ohm termination to 3.3V, so there is no need for external termination.

But the scope typically does not have the termination to 3.3V, so you would need to make sure you have the proper termination for the scope when doing the measurement of a HDMI output.

Thanks

David 

Hello David

We boust the EVB Card, DP159RSBEVM, our goal is to use it as a retimer for HDMI 2.0 signal.

In order to do that we soldered P1 HDMI connector and followed the user guide as follow:

We soldered: R16, R17, R24, R25, R134, R135, R14, R15, R18, R19, R20, R21, R22, R23.

And de-soldered: R112, R109, R111, R108, R110, R107, R106, R105, R33, R31, R32.

After that we configured the registers as follow:

Reg      Val

0xFF | 0x00         //go to first page

0x0B | 0x9B

0x0A | 0xB7

0xFF | 0x01         //go to second page

0x1A | 0x01

0x18 | 0x07

0x18 | 0x00

With these configuration the retimer only works with HDMI 1.4 signal with some devices.

We need to know how to configure the retimer for HDMI 2.0 signal and how to make It display output pattern (which didn’t not work either)

Roi

Hi,
Your issue is being reviewed by the appropriate engineer. Due to the New Years Holiday there may be a delay in response to your post. We apologize for any inconvenience.

Hi,

Please do not populate both the R24/R25 and the R134/R135. I would leave R24/R25 not populated and R134/R135 populated for the DDC snooping option. 

Getting the HDMI2.0 video out and getting the DP159 to output PRBS pattern are two separate issues. I would focus on getting the HDMI2.0 video out first. 

If you pull I2C_EN pin low (pin strap mode), HDMI_SEL pin low (HDMI mode), leave SWAP, TX_TERM_CTL, SLEW_CTL, PRE_SEL, and EQ_SEL to be No Connect, are you able to get the HDMI2.0 video out?

If not, and if you read the DP159 register 0x0B (read only, do not write), are you seeing bit 1, TMDS_CLOCK_RATIO_STATUS being set to 1? If not, then the FPGA is not properly handling the DDC read. 

If you are seeing the TMDS_CLOCK_RATIO_STATUS bit being set to 1, can you please measure the DP159 clock output (with external 50ohm termination to 3.3V) and what frequency are you seeing?

Thanks

David 

Hello David

How do you supply the clock to the Retimer?

Roi

Roi

The clock is supplied to the retimer by the FPGA on pin 11 and 12, IN_CLKP and IN_CLKN.

Thanks

David

What is yor recomendation for the clock frequency?

Roi

What is yor recomendation for the clock frequency?

Roi