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XIO2001: PCIe Trace Lengths

Part Number: XIO2001

Hi Team,

My customer is using the XIO2001, and wanted to confirm our understanding of the trace length requirements. 

Our understanding is that the clock signals need to be longer than bus signal traces, and CLKOUT6 needs to be slightly longer than those clocks provided to the downstream devices. In other words:

  • the feedback clock trace going from CLKOUT6 to CLK must be longer than the trace of CLKOUT0.
  • the trace of CLKOUT0 must be longer than the longest PCI_AD[] trace.

Do the PCI_AD traces also include any additional PCIe synchronous control signals that run in parallel to the address/data?

Regards, Diego Lewis

  • Hi Diego,

    There is no need for additional PCIe synchronous signals. The purpose of these trace length fine tuning is to make sure we have enough setup/hold time. Once your customer have their board, they can actually check these on scope to make sure they have enough margin.

    Regards ,, Nasser