Hi team.
My customer is designing the layout for SN65HVD1050.
I guess they have to care about below:
- Parallel/equal-length wiring for receiving side A, B and transmitting side Y, Z, respectively.
- Receiver A,B and Transmitter Y,Z should not be too close. So, ensure creepage distance of at least twice the line width.
- It is acceptable to set the receiver A, B and transmit Y and Z to L/S = 0.15mm/0.15mm respectively.
- For MCU connection side R,D, creepage distance should be secured at least twice the line width, and equal length wiring is not preferred.
Is there any other tips for the layout guideline to reduce niose?
It will help if there are some collaterals that explains some tips for the layout for this device.
Regards,
Ohashi
