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DS92LV18: Clarifications

Matteo Giacomello
Prodigy 490 points
Part Number: DS92LV18

I'm searching for some clarification regarding DS92LV18.

In this application TCLK and REFCLK = 20MHz, generated from an FPGA clock of about 100 MHz.

The expected Duty-Cycle will be 60% or 40% with a pretty strong accuracy (generated from a counter 3 period H and 2 L or vice versa).

These values of Duty-Cycle are the limits reported on the datasheet, they tested the device on the EVM without any problem, but wanted a further confirmation if in the real board could appear some lock issues or malfunctions.

Please let me know if from your side some problem can appear.

Thanks in advance

 

Matteo

  • +1
    TI__Guru**** 177101 points

    Matteo

    Is there a specific concern with the duty cycle?

    I would make sure keep the ratio of TCLK and REFCLK to be min of 0.95 and max of 1.05. 

    In this case, with both TCLK and REFCLK derived from the same FPGA CLK so the ratio is 1, then I do not see an issue here.

    Thanks

    David