Hello,
We are having a similar issue on a custom board design as described in this post: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/987883/dp83867cr-invalid-read-data-with-multiple-phys-on-mdio-busIn our design we are using a Zynq Ultrascale+ with three DP83867CS connected on a shared MDIO bus. There is a single pullup resistor (1.5 K) on the MDIO net. DP83867CS devices are configured in SGMII mode. Data lanes are connected to the pins 27, 28, 35 and 36. Pins 33 and 34 are used for the strap configuarion.
PHY 0 has physical address 0, RX_D0 (pin 33) and RX_D1 (pin 34) are both unconnected.
PHY 1 has physical address 1. There is a 10k pullup resistor and 2.7k pulldown resistor on RX_D0 (pin 33) and RX_D1 is floating.
PHY 2 has physical address 2. There is a 5.6k pullup resistor and 2.7k pulldown resistor on RX_D0 (pin 33) and RX_D1 is floating.
VDDIO is 2.5 V.
After the power up phase the Zynq device drives the reset pin of every PHY independently and then it tries to read the PHY Identifier Registers (PHYIDR1 and PHYIDR2). PHY0 doesn't always answer.
See attached pictures.
SLIDE 1 shows the reset phase and the delay before accessing the MDIO registers of PHY0.
SLIDE 2 shows the 32 mdc idle clock cycles before starting the read request.
SLIDE 3 shows the read request and SLIDE 4 no answer from the PHY0. There are no undershooting or overshooting on the mdc clock, the zynq is configure with minimum slew rate.
Thank you for your help
