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DS90UB962-Q1: Display black screen, LOCK status jumps

Alan Xia
Expert 4485 points
Part Number: DS90UB962-Q1
Other Parts Discussed in Thread: DS90UB933-Q1

Hi team，

My customer is PATEO and the OEM is Dongfeng.
When they only used DS90UB962, they encountered the problem that the surround view camera did not transmit images.

The connection is as follows：

The 962 chip currently used on the 8155 platform is in the mass production stage. It often encounters the problem of being unable to produce pictures. Check the 0x4D/0x4E register and there is indeed an exception. The register value printed in the exception log is as follows:

0xDB = 0x08, 0x4D = 0xc0, 0x4E = 0x0a, 0x7A = 0x02
0xDB = 0x00, 0x4D = 0xc0, 0x4E = 0x02, 0x7A = 0x00
0xDB = 0x08, 0x4D = 0xc1, 0x4E = 0x0c, 0x7A = 0x0f
0xDB = 0x08, 0x4D = 0x40, 0x4E = 0x02, 0x7A = 0x02

0x4D bit0: LOCK_STS: What are the possible reasons for the lock to be lost? We found on site that the lock status may jump repeatedly without plugging or unplugging. What are the possible reasons for this problem?

We think that there are signal integrity issues such as the quality of the wiring harness, connectors and layout, and the jitter of the reference clock input to the front-end serializer. If it is the above reasons, what tests and attempts can customers make to verify the current problem.

  • 0
    TI__Genius 11560 points

    Hi Alan,

    Thanks for providing this background information. You are correct that there are a number of potential reasons which lock could be lost here. Among these could be violations of the channel specification, jitter issues, or channel noise issues.

    Would you be able to help with the below questions on this case?

    1. Do you know if we have the schematics for these two boards? If so, would it be possible to provide it for review?
    2. You mentioned that the UB962 side is already in mass production, what is the stage of the project from PATEO? Is this still in development? 
      1. How many systems see this link stability issue?
    3. Are any scripts used for the configuration of the UB962 or UB953 in this system?

    Appreciate your help with these questions.

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    TI__Expert 4485 points

    Hi Thomas,

    Thanks for your support!

    Customers have some theoretical questions about LOCK:
    Question 1. After the deserializer is powered on, from the initialization state to the tids90ub962 0x4D register lock state, the relevant bit is set to 1. What is the logic flow of the internal judgment of the chip? What judgment conditions need to be met? What specific indicators does the chip monitor? ;
    Question 2. During operation, what conditions are met that will cause the lock to be lost and the lock register bit to be set to 0. What is the judgment logic of the chip?
    Question 3. During operation, after the lock is lost, under what circumstances will the lock be restored?

  • 0 in reply to Alan Xia
    TI__Genius 11560 points

    Hi Alan,

    For these questions could you please take a look at section 7.4.7.3 Adaptive Equalizer Algorithm of the UB962 datasheet? There are relevant details here regarding the lock mechanism. Some background below on your questions.

    1. Deserializer will increment EQ code until lock is established. Lock is established when the errors are below the programmed threshold (see 7.4.7.4.4 AEQ Threshold)
    2. Lock will be lost when errors are accumulated at the FPD receiver
    3. Lock will be restored in the same method indicated in response 1 after it is lost (also see 7.4.7.4.3 AEQ Timing)

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    TI__Expert 4485 points

    Hi Thomas，

    Here is schematic diagram：

    H97C(F6802H)_MB_V2.0_20230506_DS90UB962.pdf

    Test and int config report：

    H56 controller video output serializer related configuration.pptx

    1. Notes on attachment list files:
    H56 controller video output serializer related configuration (1).pptx: It is the AVM parameters and configuration information provided by the AVM supplier. The actual output resolution is 1920*720;
    H97C(F6802H)_MB_V2.0_20230506_DS90UB962.pdf: It is the schematic diagram of the ub962 part of our car terminal.

    2. The dump register situation during normal operation is as follows:
    2.1 ub962 car-end serializer register:

    2.2 ub933 remote AVM register:

    3. The current aeq results of the avm channel test are as follows. From the results, the quality of the wiring harness should be good.

  • 0 in reply to Alan Xia
    TI__Genius 11560 points

    Hi Alan,

    Could you clarify what serializer is used here? I see from the slides that the UB933 is referenced & in the first block diagram UB953 is referenced. 

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    TI__Genius 11560 points

    Hi Alan,

    A few additional questions on the schematic. 

    • Thanks for providing the register dump for port1 in the "normal" configuration. Does customer also have register dump in abnormal state? When failure occurs, do they check link on each RX port? Based on data below it looks like they check RX1 and RX3 registers?
      • Alan Xia said:
        0xDB = 0x08, 0x4D = 0xc0, 0x4E = 0x0a, 0x7A = 0x02
        0xDB = 0x00, 0x4D = 0xc0, 0x4E = 0x02, 0x7A = 0x00
        0xDB = 0x08, 0x4D = 0xc1, 0x4E = 0x0c, 0x7A = 0x0f
        0xDB = 0x08, 0x4D = 0x40, 0x4E = 0x02, 0x7A = 0x02
         
  • Do you have the full part number for the ESD diodes which are included near the connector?
  • Based on the MAP result from RX1 it appears to be stable, have we tested the other ports?
  • How often does customer see this issue? MAP result seems to show this  link is stable, does the problem happen intermittently (not every power cycle)? Or is there certain conditions which cause it such as temperature stress?

Best,

Thomas 

  • 0 in reply to Thomas Bejin
    TI__Expert 4485 points

    Hi Thomas，

    Sorry，it is DS90UB933-Q1

    I  I have confirmed some of your questions with the customer:

    1、ESD diodes manufacturer model ESDA0402-ULP
    The customer asked TDK to test the S parameters. The insertion loss data was not very satisfactory. I would like to ask you about the limit formula of insertion loss S21?

    2、Three inputs are connected to the customer's H56B. The connection situation is as shown in the figure below:

    The customer tested all connected three-way AEQ. Except for CHN3 which has a red part, CHN0 and CHN1 are all green.

    3、The current problem occurs intermittently, and the probability is not high. A sure way to solve it has not yet been found. When the problem occurs, the temperature is within the normal range, and it is not an extreme temperature situation.

  • 0 in reply to Thomas Bejin
    TI__Genius 11560 points

    Hi Alan,

    For the ESD diode do you know the capacitance of this diode? I couldn't find the details online.

    For the block diagram you shared, could you confirm that UB933 is for RX0 and RX1, and RX2 is the UB935? Are having lock status issues on any specific RX port?

    On the intermittent occurrence, how often is the issue seen? Is there a power cycle dependance or wait time dependance? 

    Best,

    Thomas

  • 0 in reply to Thomas Bejin
    TI__Intellectual 1330 points

    hi Thomas

    The capacitance value of this ESD tube is 0.15pF.

    The customer asked TDK to test the S parameters. The insertion loss data was not very satisfactory. I would like to ask you about the limit formula of insertion loss S21?

    Best,

    Ray

  • 0 in reply to Thomas Bejin
    TI__Genius 11560 points

    Hi Ray,

    With an impedance of 0.15pF the impact on the channel should be minimized. At 2GHz (approximate 953 forward channel rate) the effective impedance would be 530ohm, and would be better at the lower 933 rates. I don't suspect that this would cause a huge issue. Do you know if we've reviewed the layout of this customer project?

    Best,

    Thomas