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TFP410: TFP410 - Internally deterministic? Use two in pararlel for dual-link DVI?

Paul Garnett
Prodigy 10 points
Part Number: TFP410

Tool/software:

Hi,

Is the TFP410 deterministic internally - if I have two devices clocked by the same source with the same contol signals (DE/xSYNC) and I provide input data that is well-timed and synchronous, would it be reasonable to use two devices to provide a dual-link DVI connection? (CK output from the second device being unused)

Asked another way, if I fed two TFP410 devices with identical inputs would their outputs be guaranteed to be identical ie there is no metastability resolution/clock domain crossing within the part?

What if reset is asynchronous to each part? What if the two parts are accessed over I2C at different times? Do the outputs depend only on the current inputs with a fixed number of pipeline delays?

Many thanks,

Paul

  • 0
    TI__Guru**** 167756 points

    Paul

    The TFP410 has not been evaluated in a dual link application. The main issue I see with using TFP410 is the part to part skew for the dual link. Unfortunately I do not have the part to part skew data for TFP410.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Hi David,

    Thank you for the feedback, does that imply that part to part skew info is not available anywhere?

    An alternative approach for me is to use an FPGA for the serialisation, that would require TMDS drivers/redrivers/retimers etc. Are any TI products of that type chracterised for part to part skew?

    Best regards

    Paul

  • 0 in reply to Paul Garnett
    TI__Guru**** 167756 points

    Paul

    Do you have a block diagram that you can share? Assume FPGA is a AC-coupled output, then you can possibly use DP159, https://www.ti.com/lit/ds/symlink/sn65dp159.pdf as a potential solution. But with none of our DVI/HDMI parts being designed for dual DVI link purpose, we do not have the part to part skew data.

    Thanks

    David