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TLK10031: RX CRC Error

Shengyue Zhong
Intellectual 1020 points
Part Number: TLK10031

Tool/software:

Hi team,

The following screenshot is register bit14:12 traversed, the same value settings does not fit all boards and does not behave consistently, with the best performing optical module, there are still CRC errors for some PHY's Rx. The probability of a board having a problem is about 50 μs, and the replacement of the 10-Gigabit chip will improve.

We want to figure out:

1. How to solve the CRC errors?
2. For a global or RX equalization configuration, which registers can be used to optimize besides HS_SERDES_CONTROL_3?

3. TX on the other side of the RX is pre-emphasis, but it seems no effective on the PHY side. 

  • 0
    TI__Genius 16610 points

    Hi Shengyue,

    HS_SERDES_CONTROL_3 is the key register to configure HS RX EQ settings. I recommend sweeping all settings in this register (not just bits 14:12) to determine if a single configuration yields good performance across all TLK units.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1020 points

    Hi Lucas,

    Do you have some recommend settings for TLK10031? Here is register map from customer.

    xgmac_reg_dump.sh

  • 0 in reply to Shengyue Zhong
    TI__Genius 16610 points

    Hi Shengyue,

    Allow me to review the register settings and provide feedback by COB 7/3.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Genius 16610 points

    Hi Shengyue,

    I cannot see register values in this file. I can only see register addresses that are being read. Sorry I didn't see this earlier.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1020 points

    Hi Lucas,

    /*global reset*/
    GLOBAL_CONTROL_1 = 0x8610

    /*disable auto-negotiation*/
    AN_CONTROL = 0x2000

    /*turn off lt_training*/
    LT_TRAIN_CONTROL = 0x0000

    /*link setting configured manually*/
    TI_RESERVED_8020 = 0x3fff

    /*HS_SERDES_CONTROL_2*/
    HS_SERDES_CONTROL_2 = 0xa848

    /*HS_SERDES_CONTROL_3*/
    HS_SERDES_CONTROL_3 = 0xd400

    /*data path reset*/
    RESET_CONTROL |= 8

    If enable FEC function, set FEC register before data path reset
    KR_FEC_CONTROL |= 1

    Above are values of all register, other registers set to default value.

  • 0 in reply to Shengyue Zhong
    TI__Genius 17195 points

    Hello,

    Due to a US Holiday, the response to your question may be delayed. We will look into your question when we return tomorrow, July 5th. Sorry for the wait and any inconvenience it may cause.

    Thanks,

    Ryan

  • 0 in reply to Ryan Kitto
    TI__Intellectual 1020 points

    Understood. Upload values read from registers.tlk10031_reg_dump

  • 0 in reply to Shengyue Zhong
    TI__Genius 16610 points

    Hi Shengyue,

    Thank you for sharing register values. I'll review and provide feedback on Monday.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Genius 16610 points

    Hi Shengyue,

    My apologies for the delay. Can you explain the reasoning for writing TI_RESERVED_8020 = 0x3fff?

    Without knowing any details about your system/application, your other register settings seem acceptable.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1020 points
    Lucas Wolter said:
    Can you explain the reasoning for writing TI_RESERVED_8020 = 0x3fff?

    It has been mentioned in other threads, so we changed the value to see if there is any improvement.

    Below is a block diagram of this application.

    For this case, customer has tried all settings of optimized guide, you may read the .dump file in my last response. They're using the same LOT devices, but with the same parameters, you will find that about half of the chips will experience errors accumulated higher. Some devices will change with tuning parameters, but parameters are not consistent among all devices, they're wondering if they could get the matching parameters automatically.

  • 0 in reply to Shengyue Zhong
    TI__Genius 16610 points

    Hi Shengyue,

    The recommendation I see in many other threads is to write TI_RESERVED_8020 = 0x03ff, not 0x3fff. This allows link settings to be programmed manually instead of through KR training.

    I suggest you review this guide for configuring XAUI to SFI operation.

    Configuring KR devices for SFI (1).docx

    Unfortunately there is not a way to tune EQ settings automatically. To find common EQ settings across all units, I recommend sweeping all settings in register HS_SERDES_CONTROL_3 and testing BER until you find a common configuration with good performance across units.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1020 points

    Hi Lucas,

    Customer has read this file and made some values change accordingly, but still could not meet the requirement for all pcs as thousands of units been used.

  • 0 in reply to Shengyue Zhong
    TI__Genius 16610 points

    Hi Shengyue,

    Which values in HS_SERDES_CONTROL_3 have been tested? What is the failure rate with each value tested? Approximately what is the BER in each failing case?

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1020 points

    Hi Lucas,

    HS_SERDES_CONTROL_3=0xd400, you may find the BER values as below, three products had been tested. All boards are using the same register values and same optical modules. Eye diagram of TX on different board looks similar and fine to me, length of TX is 122.27mm, longer than EVM's 43.87mm and a set of vias are two differences between EVM and customized board. Btw, turn on the FEC function to lower BER is significantly.

    Test PRBS Sequence Board 1 Board 2 Results
    1 PRBS31 v027 v004 v027: RX BER exists
    v004: RX BER =0
    2 PRBS31 v021 v004 v021: RX BER_CNT=0x33, RX BER=3.8*10^-14
    v004: RX BER_CNT=0, RX BER=0
    3 PRBS31 v002 v010 v002: RX BER_CNT=0xC4, RX BER=3.2*10^-12
    v010: RX BER_CNT=0x1, RX BER=1.6*10^-15
    4 PRBS31 v002 v004 v002: RX BER_CNT=0x141, RX BER=6*10^-13
    v004: RX BER_CNT=0
    5 PRBS31 v010 v004 v010: RX BER_CNT=0, RX BER<6.7*10^-15
    v004: RX BER_CNT=0, RX BER<6.7*10^-15
    6 PRBS31 v010 v004 v010: RX BER_CNT=0x2, RX BER=1*10^-14
    v004: RX BER_CNT=0, RX BER<5.3*10^-15
    7 PRBS31 v010 v004 v010: RX BER_CNT=0x3, RX BER=5.4*10^-15
    v004: RX BER_CNT=0, RX BER<1.8*10^-15
    8 PRBS31 v002 v004 v02: RX BER_CNT=0x5A, RX BER=1.5*10^-13
    v004: RX BER_CNT=1, RX BER=1.7*10^-15
  • 0 in reply to Shengyue Zhong
    TI__Genius 16610 points

    Hi Shengyue,

    What BER are you targeting? Many of our customers target BER < 1E-12 for 10 GbE NRZ.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    TI__Intellectual 1020 points

    The target is BER < 1E-12, you can see that V002 could not meet this requirement upon the same register value, that's the part we would like to figure out or solve.

  • 0 in reply to Shengyue Zhong
    TI__Genius 16610 points

    Hi Shengyue,

    I understand and see the issue. Has testing been performed with any other values for HS_SERDES_CONTROL_3? Or has testing only been performed with 0xd400?

    Best,

    Lucas