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Original question:

[FAQ] SN75DPHY440SS: Is it okay to swap the polarity and lane order?

SN75DPHY440SS: Polarity swap with two lange CSI-2

Enrico Koeck
Prodigy 10 points
Part Number: SN75DPHY440SS

Tool/software:

(related to: https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1345522/faq-sn75dphy440ss-is-it-okay-to-swap-the-polarity-and-lane-order?tisearch=e2e-sitesearch&keymatch=SN75DPHY440SS#)

Can I swap the polarity of the lanes if I use CSI-2 with two lanes (plus clk)? The lanes are connected to D1P/N and D2P/N according to the data sheet.

  • +1
    TI__Guru*** 149685 points

    Hi,

    Even with CSI-2, the DPHY440 can't support polarity inversion, the above proposal will not work in DPHY440 default state. The high speed entry sequence consists of driving LP11->LP01->LP00 (LP->HS transition). If you flip the polarity, then the high speed entry sequence will be flipped as well and you will never able to enter into HS mode. 

    The only way it will work is that if the DPHY440 is in I2C mode and only HS mode is always enabled using the following sequence. The sequence puts the CLK and all data lanes into HS mode only.

    Write Register 0x50 with 8’h1F //Override enable for HS TX path

    Write Register 0x51 with 8’h1F //HS TX path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h1F  //Override enable for HS RX path

    Write Register 0x71 with 8’h1F  // HS RX path enabled

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Yes, I saw this answer in the other thread. Does this mean that the DPHY440 has to switch to HS mode as well (I don't see anything related in the data sheet)? And the register map in the data sheet ends with 0x11 so why are you suggesting to write something to registers beyond this address? Where is this documented?

  • 0 in reply to Enrico Koeck
    TI__Guru*** 149685 points

    Hi,

    The registers in my previous response are debugging registers that we do not publish in the DPHY440 datasheet. But these registers settings will disable DPHY440 LP mode and enable HS mode only. With DPHY440 in HS mode only, the source and the sink have to disable their LP and send the data in HS mode only as well. 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Thanks for the clarification!