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Tool/software:
Hi Ti team,
I tried to build 2 system architecture of HDMI in NB --> UB949 --> UB948 --> 1920X720 LCD
architecture1. HDMI in NB --> our UB949 board --> our UB948 board --> 1920X720 LCD,
ALP always show "Linked to Video Source: No" & HDMI freq show Not stable, but RX_5V shows detected & HPD shows true.
What may probelms result in this issue?
Panel timing (resolution 1920 X 720) that we want to light-up is as below:
I wrote the EDID as below by Deltacast, but still had no normal display:
I wrote another EDID ever post in TIE2E, but still had no normal display:
architecture 2. HDMI in NB --> UB949 EVM --> our UB948 board --> 1920X720 LCD,
UB949 EVM's OLDI output: connector: pin1: SMAD0_N, pin2: SMAD1_N, pin3: SMAD0_P, pin4: SMAD1_P,
but OLDI input in our UB948 board: connector: pin1: SMAD1_N, pin2: SMAD0_N, pin3: SMAD1_P, pin4: SMAD0_P,
and I try set register 0x49[1:0] of UB948 as 01 : Dual SWAP FPD/OLDI output, but still had no normal display.
How can I modified some setting to let our-UB948-board input meet UB949-EVM output?
ALP always show "Linked to Video Source: No" & HDMI freq show "Not stable", but RX_5V shows "detected" & HPD shows "true".
What may probelms result in this issue?
our UB949 EVM was as below:
Hi Huang,
Does the HDMI source properly recognize the HDMI sink and requested EDID?
Regarding your 949/948 connection to display - has PatGen from 948 and 949 been verified to confirm high level video timing, communication, pin out, etc?
Im not sure I fully follow the pin out that you describe. Can you illustrate further via schematic and/or diagram?
Regards,
Logan
Hi Logan,
Hope to provide with your email-address and I will mail our schematic to you.
Our EEPROM was BR24H64F-5AC-E2 for AEC-Q100 grade1.
Our HDMI source were ASUS PC BM6835 or HP 430G5, or ASUS tinker-board RK3399 Android-board.
Our panel resolution was 1920 X 720, so UB949/948 can support Max. 2K?
Regards,
Sauron
UB949 EVM FPD-Link Pin-definition:
Our HSD+2 pin-assignment in UB948 board:
Our EEPROM in UB948 board:
Besides, I tried to set 949 0x5C as 0x82 and 0x5B as 0x60 for swapping the FPD-Link pair1 & pair2 output,
but fail to link UB949 to UB948, as below.
Hi Huang -
I sent you a friend request on E2E, can you send a private message with the schematic?
Per our EVM layout - your polarity is incorrect and not the port ordering. See EVM 948 connector reference below.
Regards,
Logan
Hi Ti team,
My ALP still shows:
pixel clock was about 72MHz, port1 linked of FPD3 was false, and Active video was 1280 X 720 (1920 X 720 LCD), as beblow:
What's wrong with our UB949->UB948 system?
but we wrote 1920 X 720 as below into local EEPROM "BR24L64W" in U3 location of UB949 EVM:
Our register setting of UB949 & UB948 was as below:
Register Display - ALP Nano 1 - DS90UB949, Connector 1 Register Data Name 0x0000 0x18 I2C Device ID 0x0001 0x00 Reset 0x0003 0xFA General Configuration 0x0004 0x80 Mode Select 0x0005 0x04 I2C Master Config 0x0006 0x58 DES ID 0x0007 0xA0 SlaveID[0] 0x0008 0xB0 SlaveAlias[0] 0x0009 0x00 Reserved 0x000A 0x0A Back Channel CRC Errors 0x000B 0x00 Back Channel CRC Errors 0x000C 0x07 General Status 0x000D 0x20 GPIO[0] Config 0x000E 0x00 GPIO[1] and GPIO[2] Config 0x000F 0x00 GPIO[3] Config 0x0010 0x00 GPIO[5] and GPIO[6] Config 0x0011 0x00 GPIO[7] and GPIO[8] Config 0x0012 0x40 Datapath Control 0x0013 0x89 General Purpose Control 0x0014 0x00 BIST and DOPL Control 0x0015 0x01 I2C_VSELECT 0x0016 0x10 BCC Watchdog Control 0x0017 0x97 I2C Control 0x0018 0x7F SCL High Time 0x0019 0x7F SCL Low Time 0x001A 0x01 Datapath Control 2 0x001B 0x00 BIST BC Error Count 0x001C 0x00 GPI Pin Status 1 0x001D 0x00 GPI Pin Status 2 0x001E 0x05 TX_PORT_SEL 0x001F 0xF9 Frequency Counter 0x0020 0x07 Deserializer Capabilities 1 0x0021 0x00 Deserializer Capabilities 2 0x0022 0x25 Reserved 0x0023 0x00 Reserved 0x0024 0x00 Reserved 0x0025 0x00 Reserved 0x0026 0x00 Link Detect Control 0x0027 0x00 Reserved 0x0028 0x01 Reserved 0x0029 0x20 Reserved 0x002A 0x20 Reserved 0x002B 0xA0 Reserved 0x002C 0x00 Reserved 0x0030 0x00 SCLK_CTRL 0x0031 0x00 AUDIO_CTS0 0x0032 0x00 AUDIO_CTS1 0x0033 0x00 AUDIO_CTS2 0x0034 0x00 AUDIO_N0 0x0035 0x00 AUDIO_N1 0x0036 0x00 AUDIO_N2_COEFF 0x0037 0x00 CLK_CLEAN_STS 0x0038 0x00 Reserved 0x0039 0x00 Reserved 0x003A 0x00 Reserved 0x003B 0x00 Reserved 0x003C 0x00 Reserved 0x003D 0x00 Reserved 0x003E 0x00 Reserved 0x003F 0x00 Reserved 0x0040 0x14 Reserved 0x0041 0x5C Reserved 0x0042 0x00 Reserved 0x0043 0x00 Reserved 0x0044 0x80 Reserved 0x0045 0x00 Reserved 0x0046 0x00 Reserved 0x0047 0x00 Reserved 0x0048 0x01 APB_CTL 0x0049 0x68 APB_ADR0 0x004A 0x01 APB_ADR1 0x004B 0xD0 APB_DATA0 0x004C 0x02 APB_DATA1 0x004D 0x00 APB_DATA2 0x004E 0x00 APB_DATA3 0x004F 0x00 BRIDGE_CTL 0x0050 0x97 BRIDGE_STS 0x0051 0xA1 EDID_ID 0x0052 0x1E EDID_CFG0 0x0053 0x00 EDID_CFG1 0x0054 0x28 BRIDGE_CFG 0x0055 0x0C AUDIO_CFG 0x0056 0x00 TMDS_FIFO 0x0057 0x00 reserved 0x0058 0x00 reserved 0x0059 0x00 reserved 0x005A 0xCC DUAL_STS 0x005B 0x40 DUAL_CTL1 0x005C 0xE0 DUAL_CTL2 0x005D 0x06 FREQ_LOW 0x005E 0x44 FREQ_HIGH 0x005F 0x4A HDMI_FREQ 0x0060 0x22 SPI_TIMING1 0x0061 0x02 SPI_TIMING2 0x0062 0x00 SPI_CONFIG 0x0064 0x10 PGCTL 0x0065 0x00 PGCFG 0x0066 0x00 PGIA 0x0067 0x00 PGID 0x0068 0x00 Reserved 0x0069 0x00 Reserved 0x006A 0x00 Reserved 0x006B 0x00 Reserved 0x006C 0x00 Reserved 0x0070 0x00 SlaveID[1] 0x0071 0x00 SlaveID[2] 0x0072 0x00 SlaveID[3] 0x0073 0x00 SlaveID[4] 0x0074 0x00 SlaveID[5] 0x0075 0x00 SlaveID[6] 0x0076 0x00 SlaveID[7] 0x0077 0x00 SlaveAlias[1] 0x0078 0x00 SlaveAlias[2] 0x0079 0x00 SlaveAlias[3] 0x007A 0x00 SlaveAlias[4] 0x007B 0x00 SlaveAlias[5] 0x007C 0x00 SlaveAlias[6] 0x007D 0x00 SlaveAlias[7] 0x0080 0x00 Reserved 0x0081 0x00 Reserved 0x0082 0x00 Reserved 0x0083 0x00 Reserved 0x0084 0x00 Reserved 0x0090 0x00 Reserved 0x0091 0x00 Reserved 0x0092 0x00 Reserved 0x0093 0x00 Reserved 0x0094 0x00 Reserved 0x0098 0x00 Reserved 0x0099 0x00 Reserved 0x009A 0x00 Reserved 0x009B 0x00 Reserved 0x009C 0x00 Reserved 0x009D 0x00 Reserved 0x009E 0x00 Reserved 0x009F 0x00 Reserved 0x00A0 0x00 Reserved 0x00A1 0x00 Reserved 0x00A2 0x00 Reserved 0x00A3 0x00 Reserved 0x00C0 0x00 Reserved 0x00C1 0x00 Reserved 0x00C2 0xA8 Reserved 0x00C3 0x00 Reserved 0x00C4 0x68 Reserved 0x00C5 0x38 Reserved 0x00C6 0x00 HDCP_ICR 0x00C7 0x00 HDCP_ISR 0x00C8 0xC0 Reserved 0x00C9 0x00 Reserved 0x00CA 0x00 Reserved 0x00CB 0x00 Reserved 0x00CC 0x00 Reserved 0x00CE 0xFF Reserved 0x00D0 0x00 Reserved 0x00D1 0x00 Reserved 0x00D2 0x00 Reserved 0x00D3 0x00 Reserved 0x00E0 0x00 Reserved 0x00E1 0x00 Reserved 0x00E2 0xA8 Reserved 0x00E3 0x00 Reserved 0x00E4 0x68 Reserved 0x00E5 0x38 Reserved 0x00E6 0x00 Reserved 0x00E7 0x00 Reserved 0x00F0 0x5F HDCP_TX_ID0 0x00F1 0x55 HDCP_TX_ID1 0x00F2 0x42 HDCP_TX_ID2 0x00F3 0x39 HDCP_TX_ID3 0x00F4 0x34 HDCP_TX_ID4 0x00F5 0x39 HDCP_TX_ID5 0x00F6 0x00 Reserved 0x00F8 0x00 Reserved 0x00F9 0x00 Reserved
Register Display - ALP Nano 1 - DS90UB948, Connector 1 Register Data Name 0x0000 0x58 I2C Device ID 0x0001 0x04 Reset 0x0002 0xFC General Configuration 0 0x0003 0x7C General Configuration 1 0x0004 0xFE BCC Watchdog Control 0x0005 0x9E I2C Control 1 0x0006 0x00 I2C Control 2 0x0007 0x18 REMOTE ID 0x0008 0x00 SlaveID[0] 0x0009 0x00 SlaveID[1] 0x000A 0x00 SlaveID[2] 0x000B 0x00 SlaveID[3] 0x000C 0x00 SlaveID[4] 0x000D 0x00 SlaveID[5] 0x000E 0x00 SlaveID[6] 0x000F 0x00 SlaveID[7] 0x0010 0x00 SlaveAlias[0] 0x0011 0x00 SlaveAlias[1] 0x0012 0x00 SlaveAlias[2] 0x0013 0x00 SlaveAlias[3] 0x0014 0x00 SlaveAlias[4] 0x0015 0x00 SlaveAlias[5] 0x0016 0x00 SlaveAlias[6] 0x0017 0x00 SlaveAlias[7] 0x0018 0x00 MAILBOX_18 0x0019 0x01 MAILBOX_19 0x001A 0x09 GPIO[9] and Global GPIO Config 0x001B 0xF9 Frequency Counter 0x001C 0x3A General Status 0x001D 0x10 GPIO0 Config 0x001E 0x13 GPIO1_2 Config 0x001F 0x03 GPIO3 Config 0x0020 0x39 GPIO5_6 Config 0x0021 0x19 GPIO7_8 Config 0x0022 0x40 Datapath Control 0x0023 0x30 RX Mode Status 0x0024 0x08 BIST Control 0x0025 0x00 BIST ERROR COUNT 0x0026 0x14 SCL High Time 0x0027 0x26 SCL Low Time 0x0028 0x11 Datapath Control 2 0x0029 0x00 FRC Control 0x002A 0x00 White Balance Control 0x002B 0x00 I2S Control 0x002C 0x00 Reserved 0x002D 0x00 Reserved 0x002E 0x00 PCLK Test Mode 0x002F 0x00 Reserved 0x0030 0x00 Reserved 0x0031 0x00 Reserved 0x0032 0x90 Reserved 0x0033 0x25 Reserved 0x0034 0x61 DUAL_RX_CTL 0x0035 0x00 AEQ TEST 0x0036 0x00 Reserved 0x0037 0xA8 MODE_SEL 0x0038 0x00 Reserved 0x0039 0x00 Reserved 0x003A 0x00 I2S_DIVSEL 0x003B 0x2F Reserved 0x003C 0x20 Reserved 0x003D 0xE0 Reserved 0x003E 0x23 Reserved 0x003F 0x00 Reserved 0x0040 0x43 Reserved 0x0041 0x03 LINK ERROR COUNT 0x0042 0x03 Reserved 0x0043 0x00 HSCC_CONTROL 0x0044 0x60 ADAPTIVE EQ BYPASS 0x0045 0x88 ADAPTIVE EQ MIN MAX 0x0046 0x00 Reserved 0x0047 0x00 Reserved 0x0048 0x0F Reserved 0x0049 0x00 FPD_TX_MODE 0x004A 0x00 Reserved 0x004B 0x08 reg_4B 0x004C 0x00 Reserved 0x004D 0x00 Reserved 0x004E 0x63 Reserved 0x004F 0x00 Reserved 0x0050 0x03 Reserved 0x0051 0x10 Reserved 0x0052 0x00 areg12_2 0x0053 0x01 Reserved 0x0054 0x80 Reserved 0x0055 0x00 Reserved 0x0056 0x00 areg12_6 0x0057 0x00 areg12_7 0x0058 0x00 Reserved 0x0059 0x7F Reserved 0x005A 0x20 Reserved 0x005B 0x20 Reserved 0x005C 0x00 Reserved 0x005D 0x00 Reserved 0x005E 0x00 Reserved 0x005F 0x00 Reserved 0x0060 0x00 Reserved 0x0061 0x00 Reserved 0x0062 0x00 Reserved 0x0063 0x00 Reserved 0x0064 0x10 PGCTL 0x0065 0x00 PGCFG 0x0066 0x00 PGIA 0x0067 0x00 PGID 0x0068 0x00 PGDBG 0x0069 0x00 PGTSTDAT 0x006E 0x02 GPI Pin Status 1 0x006F 0x00 GPI Pin Status 2 0x0070 0x00 Reserved 0x0071 0x00 Reserved 0x0072 0x00 Reserved 0x0073 0x07 Reserved 0x0074 0x07 Reserved 0x0075 0x08 Reserved 0x0076 0x00 Reserved 0x0077 0x00 Reserved 0x0078 0x00 Reserved 0x0079 0x00 Reserved 0x007A 0x00 Reserved 0x007B 0x5D Reserved 0x007C 0x02 Reserved 0x0080 0x00 Reserved 0x0081 0x00 Reserved 0x0082 0x00 Reserved 0x0083 0x00 Reserved 0x0084 0x00 Reserved 0x0090 0x00 Reserved 0x0091 0x00 Reserved 0x0092 0x00 Reserved 0x0093 0x00 Reserved 0x0094 0x00 Reserved 0x0098 0x00 Reserved 0x0099 0x00 Reserved 0x009A 0x00 Reserved 0x009B 0x00 Reserved 0x009C 0x00 Reserved 0x009D 0x00 Reserved 0x009E 0x00 Reserved 0x009F 0x00 Reserved 0x00C0 0x00 Reserved 0x00C1 0x00 Reserved 0x00C3 0x00 Reserved 0x00C4 0x00 Reserved 0x00C5 0x00 Reserved 0x00C8 0xC0 Reserved 0x00C9 0x00 Reserved 0x00CA 0x00 Reserved 0x00CB 0x00 Reserved 0x00CC 0x00 Reserved 0x00E0 0x00 Reserved 0x00E1 0x00 Reserved 0x00E2 0x00 Reserved 0x00E3 0x00 Reserved 0x00E8 0x00 Reserved 0x00E9 0x00 Reserved 0x00EA 0x00 Reserved 0x00F0 0x5F RX_ID0 0x00F1 0x55 RX_ID1 0x00F2 0x42 RX_ID2 0x00F3 0x39 RX_ID3 0x00F4 0x34 RX_ID4 0x00F5 0x38 RX_ID5 0x00F6 0x00 Reserved 0x00F8 0x00 Reserved 0x00F9 0x00 Reserved
Our UB949-EVM status was as below:
Regards,
Sauron
Hi Sauron,
This is getting a bit difficult to follow with the various ALP captures indicating different statuses - without clear understanding of what was changed or current configuration.
Based on your last upload - it looks like there is actually proper CLK detected from HDMI input of 72MHz. Though it is not clear what the status is, still no output from display?
72MHz can be supported over just the single port.
Have you confirmed PG from SER side to verify video timing and confirm proper cable mapping?
Can you also comment on whether the source is identifying correct EDID?
I’ll further review the register dumps and provide further findings.
Regards,
Logan
Dear Logan,
is there some difference in EDID content between VESA and Jeida mode?
We wrote 1920x720 EDID as below, but this LCD was Jeida mode.
"949->948->LCD with Jeida mode" was only setting MAP_SEL of 948, or other setting?
Besides, hope you to share the Altium Designer schematic diagram and PCB file of 949 EVM.
Thank for your support.
Regards,
Sauron
Hi Sauron,
Jeida vs. VESA is a setting on DES side via MAP_SEL. Though - sync polarity will also need carefully matched to final display requirements.
In above - it looks like the internal SRAM EDID is selected in the menu. Can you confirm what the 949 is strapped to for EDID mode and if any init script is overriding? We need to make sure that the proper selections are made for using external EDID. For testing purposes, you might try using internal SRAM EDID as well.
The following collateral will help describe the various EDID combinations: Using EDID in FPD-Link Devices
So at this point in time - are the initial link issues between Ser and Des resolved?
Have you confirmed PG from SER side to verify video timing and confirm proper cable mapping?
Can you also comment on whether the source is identifying correct EDID?
I'll look into the availability of the 949 EVM files and get back to you.
Regards,
Logan
Dear Logan,
the below was patgen-colorbar from 949 TiEVM side with 1920X720 resolution.
Thank for your support.
Regards,
Sauron
Hi Huang,
Can you confirm if PC/HDMI source is detecting any EDID/HDMI sink at all? Is it detecting the 1280x720 resolution (default SRAM resolution).
I would suggest you first try SRAM EDID to ensure you are able to get any HDMI input, then we can iterate from there (modifying SRAM EDID to your target value, then using external EEPROM).
Can you verify the script being ran? I suspect the issue here either lies in the flashing of the EEPROM and/or the EDID mode selection on the 949 EVM.
If you probe the DDC I2C, is there I2C activity when plugging in the HDMI cable?
Regards
Logan
How do we confirm if PC/HDMI source is detecting any EDID/HDMI sink at all?
Our PC/NB become no display when connecting the Ti-949-EVM.
Thank for your support.
Regards,
Sauron
when we probed the DDC I2C of 949EVM, these devices address of 0xA0 & 0x3A will be shown.
the data of 0xA0 was: 00 FF FF FF FF FF FF 00 50 0C 00 00 00 00 00 00 00 00 01 03 80 14 00 78 0A 48 10 A2 50 46 80 25 00 48 44 00 00 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 00 04 00 50 50 D0 0A 20 28 00 01 00 00 20 00 00 00 18 00 00 00 54 00 10 29 20 20 08 00 00 20
the data of 0x3A was: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 53 00 10 89 9F 16 72 33 23 CF B8 2A 1E 51 3A 86 E7 3C 13 77 5B 05 96 80 9E F7 5C D5 54
Thank for your support.
Regards,
Sauron
Hi Huang,
It appears you are not in the proper mode for external local EEPROM mode. The 0xA0 readback above is the default SRAM EDID.
Mode_Sel0 needs set to 1 to set external local EDID, 0x4F[0] should reflect 1 (disable access to the EDID SRAM via the HDMI DDC interface).
Please find summary below: if attempting external local EEPROM, the last line needs configured.
If external EEPROM still give you trouble, you can also try overriding the internal SRAM EEPROM via I2C to avoid flashing external EEPROM.
Regards,
Logan