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DS90UB949-Q1: UB949 Linked to Video Source: always No, and EVM OLDI output can SWAP?

Part Number: DS90UB949-Q1
Other Parts Discussed in Thread: ALP

Tool/software:

Hi Ti team,

I tried to build 2 system architecture of HDMI in NB --> UB949 --> UB948 --> 1920X720 LCD

architecture1. HDMI in NB --> our UB949 board --> our UB948 board --> 1920X720 LCD, 

                       ALP always show "Linked to Video Source: No" & HDMI freq show Not stable, but RX_5V shows detected & HPD shows true.

                       What may probelms result in this issue? 

Panel timing (resolution 1920 X 720) that we want to light-up is as below:

I wrote the EDID as below by Deltacast, but still had no normal display:

I wrote another EDID ever post in TIE2E, but still had no normal display: 

architecture 2.  HDMI in NB --> UB949 EVM --> our UB948 board --> 1920X720 LCD, 

                        UB949 EVM's OLDI output:  connector:  pin1: SMAD0_N, pin2: SMAD1_N, pin3: SMAD0_P, pin4: SMAD1_P,

                        but OLDI input in our UB948 board: connector:  pin1: SMAD1_N, pin2: SMAD0_N, pin3: SMAD1_P, pin4: SMAD0_P,

                        and I try set register 0x49[1:0] of UB948 as 01 : Dual SWAP FPD/OLDI output, but still had no normal display.

                        How can I modified some setting to let our-UB948-board input meet UB949-EVM output?

                        ALP always show "Linked to Video Source: No" & HDMI freq show "Not stable", but RX_5V shows "detected" & HPD shows "true".

                        What may probelms result in this issue? 

 

our UB949 EVM was as below:

  • Hi Huang,

    Does the HDMI source properly recognize the HDMI sink and requested EDID?

    Regarding your 949/948 connection to display - has PatGen from 948 and 949 been verified to confirm high level video timing, communication, pin out, etc?

    Im not sure I fully follow the pin out that you describe. Can you illustrate further via schematic and/or diagram?

    Regards,

    Logan

  • Hi Logan, 

    Hope to provide with your email-address and I will mail our schematic to you.

    Our EEPROM was BR24H64F-5AC-E2 for AEC-Q100 grade1.

    Our HDMI source were ASUS PC BM6835 or HP 430G5, or ASUS tinker-board RK3399 Android-board.

    Our panel resolution was 1920 X 720, so UB949/948 can support Max. 2K?

    Regards,

    Sauron

    UB949 EVM FPD-Link Pin-definition:

    Our HSD+2 pin-assignment in UB948 board: 

    Our EEPROM in UB948 board:

    Besides, I tried to set 949 0x5C as 0x82 and 0x5B as 0x60  for swapping the FPD-Link pair1 & pair2 output, 

    but fail to link UB949 to UB948, as below.

  • Hi Huang  - 

    I sent you a friend request on E2E, can you send a private message with the schematic?

    Per our EVM layout - your polarity is incorrect and not the port ordering. See EVM 948 connector reference below.

    Regards, 

    Logan

  • Hi Ti team,

    My ALP still shows:

    pixel clock was about 72MHz, port1 linked of FPD3 was false, and Active video was 1280 X 720 (1920 X 720 LCD),  as beblow:

    What's wrong with our UB949->UB948 system?   

    but we wrote 1920 X 720 as below into local EEPROM "BR24L64W" in U3 location of UB949 EVM:

    Our register setting of UB949 & UB948 was as below:

    UB949 Register Setting.txt
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    Register Display - ALP Nano 1 - DS90UB949, Connector 1
    Register Data Name
    0x0000 0x18 I2C Device ID
    0x0001 0x00 Reset
    0x0003 0xFA General Configuration
    0x0004 0x80 Mode Select
    0x0005 0x04 I2C Master Config
    0x0006 0x58 DES ID
    0x0007 0xA0 SlaveID[0]
    0x0008 0xB0 SlaveAlias[0]
    0x0009 0x00 Reserved
    0x000A 0x0A Back Channel CRC Errors
    0x000B 0x00 Back Channel CRC Errors
    0x000C 0x07 General Status
    0x000D 0x20 GPIO[0] Config
    0x000E 0x00 GPIO[1] and GPIO[2] Config
    0x000F 0x00 GPIO[3] Config
    0x0010 0x00 GPIO[5] and GPIO[6] Config
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     
    UB948 Register Setting.txt
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    Register Display - ALP Nano 1 - DS90UB948, Connector 1
    Register Data Name
    0x0000 0x58 I2C Device ID
    0x0001 0x04 Reset
    0x0002 0xFC General Configuration 0
    0x0003 0x7C General Configuration 1
    0x0004 0xFE BCC Watchdog Control
    0x0005 0x9E I2C Control 1
    0x0006 0x00 I2C Control 2
    0x0007 0x18 REMOTE ID
    0x0008 0x00 SlaveID[0]
    0x0009 0x00 SlaveID[1]
    0x000A 0x00 SlaveID[2]
    0x000B 0x00 SlaveID[3]
    0x000C 0x00 SlaveID[4]
    0x000D 0x00 SlaveID[5]
    0x000E 0x00 SlaveID[6]
    0x000F 0x00 SlaveID[7]
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    Our UB949-EVM status was as below:

    Regards, 

    Sauron

  • Hi Sauron,

    This is getting a bit difficult to follow with the various ALP captures indicating different statuses - without clear understanding of what was changed or current configuration.

    Based on your last upload - it looks like there is actually proper CLK detected from HDMI input of 72MHz. Though it is not clear what the status is, still no output from display?

    72MHz can be supported over just the single port. 

    Have you confirmed PG from SER side to verify video timing and confirm proper cable mapping?

    Can you also comment on whether the source is identifying correct EDID?

    I’ll further review the register dumps and provide further findings. 

    Regards,

    Logan

  • Dear Logan,

    is there some difference in EDID content between VESA and Jeida mode?

    We wrote 1920x720 EDID as below, but this LCD was Jeida mode. 

    "949->948->LCD with Jeida mode" was only setting MAP_SEL of 948, or other setting? 

    Besides, hope you to share the Altium Designer schematic diagram and PCB file of 949 EVM.

    Thank for your support.

    Regards, 

    Sauron

  • Hi Sauron, 

    Jeida vs. VESA is a setting on DES side via MAP_SEL. Though - sync polarity will also need carefully matched to final display requirements. 

    In above - it looks like the internal SRAM EDID is selected in the menu. Can you confirm what the 949 is strapped to for EDID mode and if any init script is overriding? We need to make sure that the proper selections are made for using external EDID. For testing purposes, you might try using internal SRAM EDID as well.

    The following collateral will help describe the various EDID combinations: Using EDID in FPD-Link Devices

    So at this point in time - are the initial link issues between Ser and Des resolved?

    Have you confirmed PG from SER side to verify video timing and confirm proper cable mapping?
    Can you also comment on whether the source is identifying correct EDID?

    I'll look into the availability of the 949 EVM files and get back to you.

    Regards, 

    Logan

  • Dear Logan,

    the below was patgen-colorbar from 949 TiEVM side with 1920X720 resolution.

      

    Thank for your support.

    Regards, 

    Sauron

  • Dear Logan, 

    the Ti team suggested this EEPROM "BR24L64-W" as U3 of Ti-949EVM as below thread.

    https://e2e.ti.com/support/interface-group/interface/f/interface-forum/761596/ds90uh949-q1-read-edid-from-external-eeprom.

    So we also used  "BR24L64-W" as U3 of Ti-949EVM. 

    Thank for your support.

    Regards, 

    Sauron

  • Hi Huang, 

    Can you confirm if PC/HDMI source is detecting any EDID/HDMI sink at all? Is it detecting the 1280x720 resolution (default SRAM resolution).

    I would suggest you first try SRAM EDID to ensure you are able to get any HDMI input, then we can iterate from there (modifying SRAM EDID to your target value, then using external EEPROM).

    Can you verify the script being ran? I suspect the issue here either lies in the flashing of the EEPROM and/or the EDID mode selection on the 949 EVM. 

    If you probe the DDC I2C, is there I2C activity when plugging in the HDMI cable?

    Regards 

    Logan

  • Dear Logan, 

    How do we confirm if PC/HDMI source is detecting any EDID/HDMI sink at all? 

    Our PC/NB become no display when connecting the Ti-949-EVM.

    Thank for your support.

    Regards, 

    Sauron

  • Dear Logan, 

    when we probed the DDC I2C of 949EVM, these devices address of 0xA0 & 0x3A will be shown.

    the data of 0xA0 was: 00 FF FF FF FF FF FF 00 50 0C 00 00 00 00 00 00 00 00 01 03 80 14 00 78 0A 48 10 A2 50 46 80 25 00 48 44 00 00 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 01 00 00 04 00 50 50 D0 0A 20 28 00 01 00 00 20 00 00 00 18 00 00 00 54 00 10 29 20 20 08 00 00 20

    the data of 0x3A was: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 53 00 10 89 9F 16 72 33 23 CF B8 2A 1E 51 3A 86 E7 3C 13 77 5B 05 96 80 9E F7 5C D5 54

    Thank for your support.

    Regards, 

    Sauron

  • Hi Huang, 

    It appears you are not in the proper mode for external local EEPROM mode. The 0xA0 readback above is the default SRAM EDID. 

    Mode_Sel0 needs set to 1 to set external local EDID, 0x4F[0] should reflect 1 (disable access to the EDID SRAM via the HDMI DDC interface).

    Please find summary below: if attempting external local EEPROM, the last line needs configured. 

    If external EEPROM still give you trouble, you can also try overriding the internal SRAM EEPROM via I2C to avoid flashing external EEPROM. 

    Regards, 

    Logan