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DP83848Q-Q1: Low-Level Drivers for Ethernet Testing ( IEEE standards)

Part Number: DP83848Q-Q1

Hey Guys,

I had some questions regarding the DP83848Q-Q1. I was wondering how this device was tested to meet IEEE standards. Let em explain in more detail. So I am looking to test the physical layer of Ethernet on our new product and when I reached out to some compliance meeting companies which test 10Base - T and 100Base -TX they said that for to test the physical layer I would need a bunch of things that they could provide, but they mentioned that I would need low-level drivers.

So everyone who tests an Ethernet PHY needs to place the PHY into specific compliance test modes for each test outlined in the ANSI X3.263-1995 standard specification.   In order to place the PHY into these necessary modes, low-level drivers are needed, and must be provided by the PHY vendor.  

If the PHY vendor's part has been qualified as compliant per the Ethernet standard, then this means that the PHY vendor has already placed their PHY into the required test modes required by the standard and by definition must have drivers available to support it.   

So I'm contacting you guys to ask to speak with the engineers who originally qualified the TI Ethernet PHY that I am using.   If TI has qualified the part as compliance per the Ethernet standard, then they must have created drivers for placing the PHY into the required modes. 

As an example, to place an Intel network interface card used in our scope into the required compliance test modes, Intel provided us with GIGCONF.exe which run from MSDOS and provides a menu selection for placing the DUT into the needed modes.   

So let me know what you guys think.

Regards,

Karim Somani

  • Hi Karim,

    The DP83848 was tested at the UNH IOL for IEEE compliance. To enter the test modes described in the ANSI and IEEE standards, you will need access to the MDIO registers of the DP83848.

    Each implementation of MDIO master is different, so no low level drivers are ready to go in an MSDOS type .exe as you've described.

    What we can provide is the MDIO register settings necessary to enable each test mode.

    For those details, please see this E2E post about the ANSI test waveform generation: e2e.ti.com/.../491013

    Best Regards,
  • Hey Rob,

    So I found the 100Base - TX register information on the link you provided, but I was also looking for the 10Base - T register information. I was hoping you could direct me to that.

    Karim

  • Hey Rob,

    I see they listed the information for 100 base - TX, but I was hoping if you had information regarding the 10 Base - T test modes.

    Karim
  • Hi Karim,

    You can use register 0x1Bh within the DP83848 register field for assisting with 10BASE-T testing.

    Kind regards,
    Ross
  • Hey Ross,

    So what am I writing to the register 0x1Bh. Also if i write the specific value to the register will this cover all the cases to test 10Base-T (such as TP_IDL, MAU, Jitter, etc..) 

    Please refer the link posted in the e2e.ti.com/.../491013 

    I`d appreciate it if you could provide the information in the format form the link above. 

    Regards,

    Karim

  • Hey Ross,

    What should I write to the register to get the register in proper mode for compliance 10Base-T testing (which I believe is that it should "Output Random Data")

    Regards,

    Karim 

  • Hey Ross,

    100BASE-TX

    The following table lists the signal pattern that needs to be generated for each of the 100BASE-TX tests: Table 7-2: Test and pattern description

    Test

    Pattern

    Template

    Scrambled idles

    Differential Output Voltage

    Scrambled idles

    Signal Amplitude Symmetry

    Scrambled idles

    Rise Time

    Scrambled idles

    Fall Time

    Scrambled idles

    Rise/Fall Time Symmetry

    Scrambled idles

    Waveform Overshoot

    Scrambled idles

    Jitter

    Scrambled idles

    Duty Cycle Distortion

    Scrambled idles or 0101 pattern

    Return Loss

    Scrambled idles

     

    10BASE-T/10BASE-Te

    The following table lists the signal pattern that needs to be generated for each of the 10BASE-T/10BASE-Te tests: Table 7-3: Test and pattern description

    Test

    Pattern

    Link Pulse

    Link Pulse

    MAU

    Pseudo-random sequence

    TP_IDL

    Pseudo-random sequence

    Jitter

    Pseudo-random sequence

    Differential Voltage

    Pseudo-random sequence

    Harmonic

    All 1s or 0s

    Return Loss

    Pseudo-random sequence

    CM Voltage

    Pseudo-random sequence

    So as you can see from the test I'm doing above for 10/100Base-T. I need to know which registers to write to for each test and what to write to each register to configure the device under test for each test case. 

    Regards,

    Karim

  • Hi Karim,

    Here are the answers to your questions:

    1. Link Pulse - No register configuration needed, just observe the link pulses when you are connected to a valid partner. You could also set register 0x0h to 0x0100h to force 10BASE operation

    2. MAU - Need to have the DUT linked to the link partner in 10BASE mode, using a cable tap to observe the signals on the link, set register 0x19h bit[8] to start PRBS. You can disable Auto-MDIX and force 10BASE to make it easier to get into a correct state. Set register 0x0h to 0x0100h for 10BASE, and set register 0x19h bits[15:14] = 0b01 to force MDI.

    3. TP_IDL - same as #2 above

    4. Jitter - same as #2 above

    5. Differential Voltage - same as #2 above

    6. Harmonic - set bits[1:0] = 0b11 in register 0x1Bh

    7. Return Loss - same as #2 above

    8. CM voltage - same as #2 above

    Kind regards,
    Ross