Linux/DS90UB925Q-Q1: How to configure ds90ub925 and ds90ub940 to create output in FPD-link III format

Hello,

are you designing 925Q board or 940 board?

some comments for your reference:

1. pls refer to ub940 d/s page38, you need have correct 940 setting firstly, such as CSI port, lane number, back channel rate, etc. (http://www.ti.com/lit/ds/symlink/ds90ub940n-q1.pdf

Hello,

are you designing 925Q board or 940 board?

some comments for your reference:

1. pls refer to ub940 d/s page38, you need have correct 940 setting firstly, such as CSI port, lane number, back channel rate, etc. (http://www.ti.com/lit/ds/symlink/ds90ub940n-q1.pdf

2. For 925 side, you also can use the mode_sel (d/s, page23 http://www.ti.com/lit/ds/symlink/ds90ub925q-q1.pdf) to set the correct working mode.

3. basically, if NOT special GPIOs are required, the link between 925 and 940 can work well. you can measure the 940's CSI_CLK output and data lane output, any signal?

4. pls note the 940, it has default input video timing request described as below (in d/s), pls make sure your video timing is ok. also, you can use the pattern generation in 925 side to verify the link whether it is reliable.

7.4.4 Input Display Timing
The DS90UB940N-Q1 has built-in support that can detect the incoming video format extracted from the FPD-Link
III data stream(s) and automatically generate the CSI-2 output timing parameters accordingly. The input video
format detection is derived from progressive display resolutions based on the CEA−861D specification. The
engineer can measure the internal VS and DE signals to determine the video data and frame rates. The device
supports up to 4095 pixels per line.
For system implementations with custom video resolutions, system designers should either program the TIvalidated
D-PHY timing parameters provided in the Configuring DS90UH940N-Q1 MIPI® D-PHY timing
parameters application report (SNLA303), or validate the auto-generated parameters.

best regards,

Steven