SN65DSI86: DSI to DP compliance test items failed of Pre-Emphasis

Hi Ti team member:

I am a SW member from WNC.

What the value should be filled for ML_TX_MODE (0x96) while compliance test?

Thanks.

ML_TX_MODE description: 

0000 = Main Link Off (default)
0001 = Normal mode (Idle pattern or active video)
0010 = TPS1
0011 = TPS2
0100 = TPS3
0101 = PRBS7
0110 = HBR2 Compliance Eye Pattern
0111 = Symbol Error Rate Measurement Pattern
1000 = 80-bit Custom Pattern
1001 = Fast Link Training
1010 = Semi-Auto Link Training.
1011 = Redriver Semi-Auto Link Training

Chihyang, WNC

Hi Ti team:

Does this SN65DSI86 bridge support DPR100 (AUX controller)?

If yes, which registers and values should be configured?

Thanks

Chihyang, WNC

Hello Chihyang,

We have assigned an engineer to this thread, but response will be delayed due to holidays.

Regards,

JMMN

Hi JMMN:

Thanks.

When will we probably get any suggestion for this topic?

Chihyang, WNC

Hi Chihyang,

Sorry for the delay, we hope to provide some suggestions for you on this topic by Monday.

Regards,

I.K. 

Chihyang

The pre-emphasis settings are updated by hardware during link training.  For compliance testing, software will need to change the pre-emphasis settings.

The level is programmed through register 0x93 bit [7:6]. 

But the actual value associated with each level is programmed through the DP Link Training LUT registers (Table 28 in the datasheet).

Thanks

David

Hi David:

Thanks. But something I am not sure about:

From the Lecroy report provided by Albert/WNC:

SA8155 Native DP_lane 0_RBR~HBR2 3.9dB_25.pdf

We selected 0b0110 (HBR2 Compliance Eye Pattern) for ML_TX_MODE (0x96) register in this test case.

And the many PreEmp test items are failed 

----------------------------------------

example:

PreEmp, 0dB 400mV

current value: 2.412 dB

Test Criteria: x <= 250 mdB

------------------------------------------

For this compliance test case, should we refer DP Link Training LUT registers (Table 28) to adjust it?

Thanks.

WNC, Chihyang

Hi David:

The following items can't be test too.

1. Jitter

2. RBR~HBR eye diagram

3. Main Link Frequency Max (ppm)

WNC, Albert

Albert

PreEmp, 0dB 400mV is both SWING and Pre-emphasis level 0.

So you need to set register 0x93 bit [7:6] to 00 for Pre-emphasis level 0 and register 0x94 bit[1:0] to 00 for SWING level 0. You may also need to tune the actual Pre-emphasis and SWING value using the Link Training Registers.

RBR is 1.6G and HBR is 2.7G, did you change the data rate in the DSI86 registers?

Thanks

David

Hi David,

RBR is 1.6G and HBR is 2.7G, did you change the data rate in the DSI86 registers?

No, the oscilloscope will request the DSI86 to change the pattern & data rate through the AUX interface.

So we need DSI86 can auto change the test pattern. The pattern include below table's pattern.

Can you help to provide the register setting to me?

Albert

Please refer to this app note: http://www.ti.com/lit/an/slla425/slla425.pdf, section 4.1 for the data rate programming.

For data pattern programming, please program the ML_TX_MODE field at register 0x96.

Thanks

David

Hi David:

Our goal is do SN65DSI86 compliance test with "AUX controller DPR100".

Can SN65DSI86 support "AUX controller DPR100" and switch patterns automatically?

If yes, which value should be filled in ML_TX_MODE?

If no, tell us and we will just find another way out.

Thank you.

Chihyang, WNC