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DS90UB934-Q1: HSYNC/VSYNC signals not present

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Replies: 38

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Part Number: DS90UB934-Q1

I am using the 934 deserializer in conjunction with the 935 serializer connected to a CSI-2 (MIPI) image sensor. The SerDes is in DVP mode with an external FrameSync sourced from the deserializer end.

The video data out of the deserializer goes between active and blanking (all zeros) as expected, but HSYNC is always high and VSYNC is always low on their respective deserializer pins.

The issue is similar to this post: https://e2e.ti.com/support/interface/f/138/t/735724 

but I am using a CSI serializer so I can't verify SYNC presence in the same way.

I've attached the register settings of the SerDes devices, and noted the ones that have changed between resetting the chips and my initialization functions. Those register settings can be viewed in the table file below. Any other registers not mention can be assumed to be default.

0385.FS Reg Drop.pdf

Any advice would be greatly appreciated.

Regards,

Sam Shafer



  • Hi Sam,

    Is this the same issue from here: https://e2e.ti.com/support/interface/f/138/t/874818?tisearch=e2e-sitesearch&keymatch=%2520user%253A425383

    If so, we can close this thread and discuss the issues at the old thread.

    Best,

    Jiashow

  • In reply to Jiashow Ho:

    Jaishow,

    I don't believe these issues are the same; the aforementioned issue is with remote GPIO signal integrity on the back channel. This is a complete lack of signal through the forward channel. Unless the Deserializer's ability to compute HSYNC/VSYNC signals depends on the sensors frame sync, the issues are indeed separate.

    I'm not sure what factors lead to the generation the H/VSYNC signals on the deserializer end. The datasheet for the 934 does not explain that functionality. Any further documentation or explanation would help me in tracking down the source of this error.

    Thanks,

    Sam

  • In reply to Samuel Shafer:

    Update:

    I resolved the issue of the aforementioned post, but HSYNC and VSYNC signals are still no where to be found.

  • In reply to Samuel Shafer:

    Here is a screen capture of the waveforms on the various 934 deserializer pins while the system is running.  Datain = ROUT. Notice how HSYNC stays high, VSYNC stays low. They have yet to ever change.

  • In reply to Samuel Shafer:

    Hi Sam,

    Can you first check if valid CSI input is detected by the 935?

    You can check the packet header, payload, and CSI errors at 935 reg 0x5C, 0x61, 0x62, 0x63.

    Best,

    Jiashow

  • In reply to Jiashow Ho:

    Here are the results to that test:

    SZR regs:

    0x5C is [0], 0x61 is [0] , 0x62 is [0] , 0x63 is [0]

    Update: I also ran a test on the following DSZ regs:

    0x55 [0],0x56 [0], 0xD0 [0], 0xD8 [0], 0xD9 [0], 0xDA [0], 0xDB [0]

  • In reply to Jiashow Ho:

    It seems that the error is not caused my the MIPI interface between sensor and serializer. I suspect the source is th  deserializer, but cannot yet confirm.

    To reiterate, the register commands I've changed are: [Reg,Data]

    DSZ init
    [DSZ_RESET,0x7],[FPD3_PORT_SEL,0x11],[PORT_CONFIG,0x7B],[BCC_CONFIG,0xD8] ],[DSZ_CONFIG,0x3E],[FS_CTL,0x80],[GPIO0_PIN_CTL,0x01],[GPIO1_PIN_CTL,0x00],[BC_GPIO_CTL0,0x10],[BC_GPIO_CTL1,0x32],[BIST_CTL,0x00],[FPD3_PORT_SEL,0x01]

    SZR init
    [0x01,0x04],[0x02,0x03],[0x03,0x15] ,[0x04,0x05],[0x05,0x03],[0x0D,0x32],[0x0E,0x30],[0x10,0x0],[0x11,0x0] ,[0x17,0x0],[0x18,0x0],[0x20,0x00],[0x21,0x00],[0x32,0xC9],[0x49,0x28]

  • Update: I analyzed the MIPI signal coming out of the sensor. It appears to be correct in terms of line and frame data length, as well as short packet placement for indicating frame start and stop. I'll attach screen captioned scope captures.

    An issue I did notice is that the frame sync signal into the sensor is not synchronizing with the data coming out of the sensor. This indicated that the issue lies within the sensor rather than the SerDes components. I reached out to the sensor manufacturer for help and will keep this thread updated with any relevant information they provide.

    Attached are a few images of the MIPI signal:

    1) MIPI frame's first line signal

    2) MIPI end of frame signal

    3) Zoom on end of frame signal's data portion

    4) Frame start short packet (followed by blanking until first valid line)

    5) Zoomed in on frame start's packet data(Left part is fixed, left middle  is counting, right middle is fixed,  right part  may be checksumming)

  • In reply to Samuel Shafer:

    Update: We fixed the synchonisation on the sensor end. Still no H/VSYNC on the Des end.

    Image below shows frame start signal on every clock rising edge

    Pink = Clock, Blue = Mipi Data

  • In reply to Samuel Shafer:

    Hi Samuel,

    The sensor information should be available in 953 registers 0x5C, 0x61, 0x62, 0x63 if it's valid. Are they still reading 0x00 even after you fixed the synchronization? Are you getting consistent, error-free lock?

     Best,

    Jiashow

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