SN74LVC1G125-Q1: design BUG

YEPENG ZHANG

Part Number: SN74LVC1G125-Q1

Hello Ti engineers，

there is a SN74LVC1G125-Q1 in our design，the OE is tie to GND ，and A is from outside device (SPI_MISO) , and Y connect to MCU ，we found that when A is tristate，Y is low，but MCU cannot control the AURIX_SPI3_MISO_3V3 (this signal is reuse with other chip)，We want to know if this is reasonable，and when A be pull down， whether the MCU can control this Y net.

8 months ago

0 Clemens Ladisch 8 months ago

Guru 257450 points

When the signal at the A input is floating, it will still be read as low or high, you just do not know which. (And you should never do this; see [FAQ] How does a slow or floating input affect a CMOS device?)

If you want to make the Y output tristate, you have to pull /OE high.

0 YEPENG ZHANG 8 months ago in reply to Clemens Ladisch

Prodigy 85 points

We want to know if the MCU can forcibly pull up the network when the output of SN74 is low due to a pull-down resistor of 10K in Y. We have actually tested it and found that it is not possible. Is it because the output driving ability of SN74 is very strong?

+1 Clemens Ladisch 8 months ago in reply to YEPENG ZHANG

Guru 257450 points

The pull-down resistor has no effect on the output signal; the Y output will actively drive either low or high, and indeed is very strong.

0 YEPENG ZHANG 8 months ago in reply to Clemens Ladisch

Prodigy 85 points

I see. Thank you very much

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SN74LVC1G125-Q1: design BUG