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SN74LVC1G125-Q1: design BUG

Part Number: SN74LVC1G125-Q1

Hello Ti engineers,

   there is a  SN74LVC1G125-Q1 in our design,the OE is tie to GND ,and A is from outside device (SPI_MISO) , and Y connect to MCU ,we found that when A is tristate,Y is low,but MCU cannot control the AURIX_SPI3_MISO_3V3 (this signal is reuse with other chip),We want to know if this is reasonable,and when A  be pull down,  whether the MCU can control this Y net.