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SN74LVC1G125: Why OUTPUT is pulled high when PinA reach to 756mV

Part Number: SN74LVC1G125
Other Parts Discussed in Thread: TPS3839, TLV840, SN74LVC1G17

Tool/software:

Hi Team,

This is FAE Jayden, my customer is using SN74LVC1G125, and they have one question about this device.

The Schematic is as below: 

The application conditions are as follows: PinA uses an RC delay circuit, and the PinY output is pulled up to VCC through 4.75kohm.ZTE discovered that when the input of the PinA has not yet reached VIH=0.65*VCC, the Y pin outputs a high level, causing the subsequent devices to reset prematurely. The waveform is as below:

CH1-OUTPUT Y CH2-PINA CH3-ignore Ch4-1.8V VCC

Could you help check the root cause? Many Thanks!

Best regard

Jayden

  • The output can switch high for any input voltage above VIL. (In practice, the switching threshold is likely to be near VCC/2.)

    In any case, correct operation of the A and Y pins is guaranteed only for supply voltages of at least 1.65 V. And this slow input signal exceeds the Δt/Δv limit.

    You should use a voltage supervisor like the TPS3839 or TLV840. If cost is more important than reliability, just increase R2.

  • Hi Clemens,

    Thanks for your reply. My customer has increased R2 to 10k. 

    As you mentioned, the slow input signal VCC exceeds the Δt/Δv limit. As you can see, due to the existence of the RC delay circuit, the input voltage of pin A rises slowly during the power-on process. It takes about 20ms for VA to rise from 0.6V to 1V. At this time, the buffer may be in an uncertain state.

    Is there any reliability risk in the above application? The product will be powered on and off about 10,000 times in its entire life cycle.

    Brs

    Jayden

  • A Schmitt-trigger buffer like the SN74LVC1G17 will be better able to handle a slow signal; see [FAQ] How does a slow or floating input affect a CMOS device?

    (This will not remove the uncertainy at very low voltages.)