SN74AUP2G00-Q1: How to design the gate's output?

Manwoo Kim

Intellectual 565 points

Part Number: SN74AUP2G00-Q1

Hello,

I have some qeustions about NAND Gate(SN74AUP2G00-Q1).

1. There is Function table in the datasheet, but there is no information that two inputs are "X".

What's the output level when two inputs logic is "X"?

2. If we want that NAND gate's output goes "L" when two inputs are "H", How we design the output default level? (Actually, we want that output level is "H" if any of two inputs are not "H".)

Which is better pull-up or pull-down? Is floating best? If we sholud design using pull-up or pull-down resistor, could you recommend the value of resistor?

Thanks,

Manwoo Kim

over 4 years ago

0 Clemens Ladisch over 4 years ago

Guru 261280 points

"X" is not a logic level; it is a placeholder that stands for "either H or L". (In the SN74AUP2G00-Q1 datasheet, the "X" is pointless and could just use "H" instead, because there already is a table entry for "L"+"L".)

Why are you mentioning pull-up resistors? Do you expect that some input signal will ever float? (That would be forbidden.)

0 Manwoo Kim over 4 years ago in reply to Clemens Ladisch

Intellectual 565 points

Hello,

Thanks for your answer.

As you know, If we use 1.8 voltage level as a Vcc, the input of NAND gate can detect high when input voltage level is higher than 1.17V(0.65*Vcc).

Also, It can detect low when input voltage level is lower than 0.63V(0.35*Vcc). So, I wonder how NAND gate work when input level is between 0.63V and 1.17V.

Plus, As you mentioned, I think input signal can be floating or some level(0.63V~1.17V).

Thanks,

Manwoo Kim

0 Clemens Ladisch over 4 years ago in reply to Manwoo Kim

Guru 261280 points

The inputs must always be at a valid logic level. See [FAQ] How does a slow or floating input affect a CMOS device?

If a signal can float, then you must add a pull-up or pull-down resistor. The actual values does not really matter; typically, 10 kΩ is used.

0 Manwoo Kim over 4 years ago in reply to Clemens Ladisch

Intellectual 565 points

Thanks for your reply.

As I said, we want that output of NAND gate should detect "H" except that two inputs are "H".

Should we have pull-down resistors at input line?

How about output pin? Should we have a pull-up resistor at output line?

Could you please give me some comment for our case?

Thanks,

Manwoo Kim

0 Clemens Ladisch over 4 years ago in reply to Manwoo Kim

Guru 261280 points

Please specifiy the desired output for each input combination (that can actually happen):

low      low      :
low      high     :
low      floating :
high     low      :
high     high     :
high     floating :
floating low    :
floating high :
floating floating :

0 Manwoo Kim over 4 years ago in reply to Clemens Ladisch

Intellectual 565 points

I filled in all the cases below

low      low      : High
low      high     : High
low      floating : High
high     low      : High
high     high     : Low
high     floating : High
floating low    : High
floating high : High
floating floating : High

Thanks

Manwoo Kim

0 Clemens Ladisch over 4 years ago in reply to Manwoo Kim

Guru 261280 points

You need pull-down resistors on both inputs.

As long as the NAND gate is powered, it will output a voltage, so you do not need an output pull-up resistor.

0 Manwoo Kim over 4 years ago in reply to Clemens Ladisch

Intellectual 565 points

Thanks!

When NAND gate is powered, what's the output level's voltage?

Manwoo Kim

0 Clemens Ladisch over 4 years ago in reply to Manwoo Kim

Guru 261280 points

When connected to some CMOS input, the voltage is at the rails (V_CC or GND). If you put an additional load on the output, see the V_OL/V_OH specifications.

0 Manwoo Kim over 4 years ago in reply to Clemens Ladisch

Intellectual 565 points

Thanks,

Actually, I don't understand your comment.

Does "the voltage is at the rails (Vcc or GND)" means output level can be "H" or "L"?

Manwoo Kim

0 Clemens Ladisch over 4 years ago in reply to Manwoo Kim

Guru 261280 points

Yes, the output is either H or L.

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SN74AUP2G00-Q1: How to design the gate's output?