SN74LVC1G08-Q1: DESIGN REVIEW

Hi Melbin,

Thanks for the opportunity to review your schematics.

It looks like you're using one AND gate as a buffer (A tied high) and the other to AND the buffered output and the signal INH_ENA_ISO together.

The parts that I can see on the schematic are fine. You can get rid of R2623 and short pin 1 of U348 directly to V_CAN_VIO. You might consider swapping that AND gate to a Schmitt-trigger buffer, depending on the input signal characteristics at PMIC_SS2. If it's a relatively slow signal, a Schmitt-trigger buffer will prevent errouneous outputs and added power consumption. SN74LVC1G17-Q1 would be a good choice.

I can't see the signals at PMIC_SS2 or INH_ENA_ISO, so I don't know if they are good or not. I would recommend signals that are near the power rails (0V and 3.3V) for logic low and high, and transition quickly between those rails (max transition time of 33ns).

Additionally, I can't see the load at OUT_1. I would recommend a light load (15pF to 50pF) and up to 24mA current drive.

Hey Melbin,

To add to what Clemens mentioned, if this topology is needed then you could use a device like the SN74LVC2G08-Q1.