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Frequent questions

  • [FAQ] How do I terminate any unused channels of a logic device?

    FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ CMOS Inputs All CMOS inputs must be terminated at either Vcc or Ground. The inputs of a CMOS device are high-impedance. These terminations can be through a resistor (for example…

  • [FAQ] Are there voltage level translation / level shifter device recommendations for the industry standard interfaces like GPIO, SPI, UART, I2C, MDIO, RGMII, I2S etc?

    FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ Here are the voltage level translation device recommendations for various industry standard interfaces: Interface Recommended Device 3.6V Maximum 5.5V Maximum…

  • [FAQ] What is the default output of a latched device? (Flip-Flop, latch, register)

    FAQ: Logic and Voltage Translation > Output Parameters >> Current FAQ Flip-flops, latches, and registers do not have a default state on power up. The output is in an 'unknown' state until data is clocked through. Because of this, SPICE simulation models…

  • [FAQ] How does a slow or floating input affect a CMOS device?

    FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ There are two primary issues associated with slow and floating inputs. Not sure what a 'floating input' is? Please see our FAQ: What is a floating input or floating node? (1) Shoot…

  • [FAQ] If the OE pin is asserted to maintain Hi-Z at the IO, will it disconnect the internal pull-up resistors in TXS devices?

    FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ Yes, the internal pull-up resistors are disconnected once OE is asserted(to enable High impedance on the IO ports) Additionally, if the device supports Vcc isolation feature …

  • [FAQ] Can the input voltage (Vi) to my logic device be higher than the supply voltage (Vcc)?

    FAQ: Logic and Voltage Translation > Input Parameters >> Current FAQ This question is really about the input structure of a logic device. There are primarily two types of CMOS input structures - one with a positive clamping diode, and one without…

  • [FAQ] Where do I connect the thermal pad of the logic QFN devices?

    FAQ: Logic and Voltage Translation > Power and Thermals >> Current FAQ Some datasheets do not specify what should be done with the thermal pad, such as in the image below: The thermal pad is recommended to be soldered to the PCB and electrically…

  • [FAQ] What is the maximum capacitive load that a logic device can drive?

    Other Parts Discussed in Thread: SN74LVC2G34 FAQ: Logic and Voltage Translation > Output Parameters >> Current FAQ There are a few issues with trying to determine a maximum capacitive load for a standard CMOS logic device. First is propagation delay…

  • [FAQ] Why does a logic device's part number have an E4/G4 suffix?

    FAQ: Logic and Voltage Translation > Quality and Manufacturing >> Current FAQ In short, there will be no difference between a device labelled SN74xxG4 and SN74xx. Historically, G4 and E4 suffixes meant that the devices were rated to be "Green" or…

  • [FAQ] What is the difference between TXS TXB and LSF devices?

    FAQ: Logic and Voltage Translation > Voltage Translators >> Current FAQ

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