TMS570LS3137: Enabling ECC in Flash wrapper vs in the CPU

Hi, our expert is out of the office. Please expect a delayed response.

Hi Chuck,

The main program memory is protected by the SECDED circuit implemented inside the Cortex-R4 CPU. All OTP and the FEE memory (bank 7) is protected by dedicated SECDED logic inside the Flash wrapper. Both the SECDED logic implementations use Error Correction Codes (ECC) for correcting single-bit errors and for detecting double-bit errors in the values read from the flash arrays.

The ECC protection for accesses to the EEPROM emulation flash bank and OTP flash banks can be enabled by writing 0xA to the EDACEN field of the flash module’s Error Correction Control Register 1 (FEDACCTRL1).

Hi QJ,

I understand what you're saying above, but no I cannot decode from it the answer to my following question:

Does the above quoted text saying that the FEDACCTRL1->ECDACEN bits should be enabled by writing 0xA to it before enabling bit #25 of the Auxiliary Control Register?

Thanks.

Hi Chuck,

No, the ECC protection logic for EEPROM and OTP is implemented in flash wrapper only. Setting bit 25 of ARM ACTLR register (Auxiliary Control Register) is to enable the SECDED logic in CPU which is used for main program flash (bank0, and bank1).

Hi QJ,

I'm very sorry, I've mixed up between the EEPROM/OTP (starting at 0xF0000000) and the main program flash (starting at 0x0 for 3MB).

What I'm trying to do is to generate an ECC double-bit error by simulating a bad main program flash, having 2 bits flipped at a given address.

Could you please provide more insight? I'm not using Halcogen so need a procedure of doing so.

Thank you very much.

Hi QJ,

I was following procedure found in spnu499c para. 5.6.2.6 ECC Data Correction Diagnostic Test Mode: DIAG_MODE = 7, using FPAR_OVR_bit.DAT_INV_PAR = 0x03 that was undefined in para. 5.3.3 Syndrome Table, therefore to simulate multi-bit uncorrectable Flash ECC error.

The result is that I'm getting an Abort exception rather than an uncorrected ESM error that should activate the nERROR signal pin.

What should be the ESM error generated in this case?

Since this is an uncorrected ECC error, which is a severe ESM Group2 or Group3 unmaskable error, why the nERROR signal pin was not asserted?

Thanks.

QJ,

After reading mirrored Flash location at address 0x20000000, a CPU abort exception was generated and the following data fault registers were captured, which seem to be correct:

• DFAR=0x20000000
• DFSR=0x1008

The only issue is that no ESM error was generated for this double-bit simulated error. All ESMSR1, 2, 3 and 4 registers are 0x00000000 following the abort exception.

In the ACTLR ARM CPU register, the following have been configured to pass on errors to CPU:

• Bit25=1 is ATCM ECC check enable (main flash array)
• Bit0=1 is ATCM external error into CPU enable

This critical error could not be masked, so what could be the reason?

Thanks for the great help QJ,

Only one thing was missing: the procedure found in spnu499c para. 5.6.2.6 didn't mention that the Flash Error Detection and Correction Control Register 1 (FEDACCTRL1) has to be configured, so that the CPU ECC Flash errors event signals will be unblocked.

Adding this unblocking instruction solves the problem.

Best regards!

QJ,

One more question: Should this line be part of the application even when not performing Flash ECC checking test?

FEDACCTRL1 = 0x000A060AU;

If I leave this line without performing Flash ECC checking test, the application crashes.

If I don't leave it with the application, are Flash ECC errors will still be reported to the CPU if happens?

Thanks.