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AM2434: DDR initialization with DDR_VTT_EN on a GPIO different than L18

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

I cannot find where, in the bootloader or SysConfig generated code, the DDR_VTT_EN GPIO is driven high.

As recommended I have created a custom bootloader based on sbl_null taken from AM64X SDK where DDR is supposed to have been initialized properly.

Anyway, I have to add my custom GPIO to drive DDR_VTT_EN high and this cannot be done before System_init() because pinmux is not configured yet.

But if I turn high the GPIO after System_init() it won't work because System_init() contains DDR_Init() and it will fail due to DDR_VTT_EN still low.

I am wondering how sbl_null bootloader is driving high DDR_VTT_EN:

  • is it done by SysFw self ? (in such case how to change GPIO L18 to a different one ?)
  • is it included in some board configuration requests passed from the bootloader to SysFw ? (where exactely ?)

Looking forward.

   Andrea

  • Hi Andrea,

    I am a little bit confused here. The L18 (GPIO0_12, OSPI0_CSn1) is used in AM243x/AM64x EVM for "VTT 0.6V regulator Enable". Does this have anything to do with the DDR_init? I do not see any reference to L18, GPIO0_12 or OSPI0_CSn1 in the syscfg generated files or in the MCU+ SDK code.

    Best regards,

    Ming

  • Hi Ming,

       L18 is DDR_VTT_EN input of 1,8V to 3,3V level translator whose output is DDR_VTT_EN_3V3 responsible for VTT SUPPLY FOR DDR4.

    So, in our custom board we need to raise a GPIO different than L18 and we have to do it before DDR_init otherwise it will fail becase DDR is not powered.

    When I add DDR in SysConfig I will get a generated code with System_init() calling PinMux_init() and then DDR_init().

    So there is no chance to raise a GPIO between PinMux_init() and DDR_init() because the code is generated automatically by SysConfig.

    By the way, I am really tring to figure out where L18 is raised high on AM243x/AM64x EVM to do the same with my custom GPIO:

    • is it a board configuration passed to SysFw ?
    • is it embedded in the SysFw ?

    Looking forward

        Andrea

  • Hi Andrea,

    I checked with the expert of the sysconfig for DDR. He confirmed that the DDR_VTT_EN is not done in sysconfig. It is possible passed to SysFW by "TISCI_DEV_DDR16SS0" in gSocModules defined in ti_power_clock_config.c. I will need to confirm that with the SysFW team.

    There is another possibility that the DDR_VTT_EN is always on for AM64x/AM243x EVM.

    Best regards,

    Ming

  • Thanks Ming,

       I have just found that ti_power_clock_config.c calls SOC_moduleClockEnable passing TISCI_DEV_DDR16SS0 as module to be turned on, but there is no mention of such L18 GPIO that, I suppose, would be embedded in SysFW.

    Anyway, it is a strong limitation since L18 can be used for other functions (OSPI for instance).

    I would expect to be a configurable pin not just hard-coded in SysFw

    Looking forward

        Andrea

  • Hi Andrea,

    After some digging, I concluded that the DDR_VTT_EN is always enabled. It is not dynamically enabled in neither SysFW nor Sysconfig generated code. Here are what I did:

    1. Measure the voltage at TP48 (VDDR_VTT). It is always 0.6V for NO_BOOT mode, SBL_NULL with  initialization or SBL_NULL without DDR initialization on AM243x EVM

    2. I checked the settings for GPIO0_12 (0x600018 and 0x600010) for NO_BOOT mode, SBL_NULL with  initialization or SBL_NULL without DDR initialization on AM64x/Am243x EVM. They are all the same: 0x00000000 and 0xFFFFFFFF.

    The above observation means the that at least for the AM243x EVM, the DDR_VTT_EN was not set by the software (SysFW or Sysconfig generated code).

    In the CCS 11.1 GEL file, the Enable_VTT_Regulator() was defined in C:\ti\ccs1110\ccs\ccs_base\emulation\gel\AM24x\AM24_DDRSS\AM24_DDRSS_Config.gel, but it has never been used. It also indirectly confirms that the DDR_VTT_EN was hardwired on AM243x EVM.

    I think it is a bug for the sysconfig. I will file a ticket against the sysconfig for DDR. Hopefully we can fix it in next release.

    Best regards,

    Ming