I´m using Async EMIF and I have observed some behaviour regarding the Write Enable signal which I don't understand.
The problem is basically observed between consecutive writings. The time between assertions of WE (Write Enable) signal is surprisingly high (around 450 nseg @ EMIF clock of 50 MHz) but is also variable.
Normally I am transfering the data using a for loop of 16 bits (which is also the width of the EMIF interface configuration) elements. The processor is working at 100 MHz so I wouldn't expect such delay as a consecuence of the mentioned loop.
for (i = 0; i < 12U; i++)
{
*(Destination + i) = *(Origin + i); //Destination and origin are memory pointers (Uint16_t*).
}
It is also worth to mention that each 4 transfers the WE transition is pretty short (marked in green) compare to the others (marked in blue).
We have also tried to use consecutive writings without the for loop with no changes….
The only thing observed that seems to have some effect is to order bigger transactions (with a cast for example) although the width of the EMIF bus is still 16 bits.
for (i = 0; i < 3U; i++)
{
*((uint64*) Destination + i) = *((uint64*) origin + i); //Destination and origin are memory pointers (Uint16_t*).
}
In this case it is observed a reduction between the forementioned consecutive WE assertions. This reduction is observed normally grouped in chunks of four transactions (16 bits each) and then comes a larger one (except at the beginning which are only two "fast" transaction before the "slow" one.
I am guessing that this behaviour may have someting to do with an internal FIFO of the EMIF peripheral but the delay mentioned seems quite high to me and limits the possible throughput of the interface. The "slow" time between transactions is the almost the same as the transaction itself.
If anyone could give me some explanation or guidance on how to improve this I would be grateful :)
Thanks in advance.
