RM57L843: How to do fault injection for PBIST and LBIST

Hi Shenruming,

Started working on your issue and we will get back to you on this soon.

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Thanks & regards,
Jagadish.

Hi Jagadish,

As you replied in email, "self-test fault injection may only be done by modifying CCMUYR = 0x9U in functions such as ccmSelfCheck". But we can't find the function "ccmSelfCheck" and set "CCMUYR = 0x9U".

Can't we just use SafetTI Diagnostic Library to inject fault into functions "SL_SelfTest_PBIST/SL_SelfTest_STC"?

Hello Jagadish,

Any update for this topic?

Apologies for the delay.

Reassigned to QJ.

Hi QJ,

Do we have any method to force the errors which can be detected by functions SL_SelfTest_PBIST and SL_SelfTest_STC?

For C2000, there're detailed introduction of HWBIST/MBIST in specialized documents as below:

Are there similar documents about LBIST/PBIST test for RM57L843 device?

Thanks so much!

Hi QJ,

It seems that setting FAULT_INS field of STCSCSCR register is equal to selecting the test type "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" for function SL_SelfTest_STC.

If so, why did you say "The LBIST and PBIST don't have fault injection"?

CPU selftest is not exactly same as STC self-check. STC is a controller to test CPU core using LBIST controller which is implemented on the CPU.

STC self-check is to check the STC rather than LBIST. 

Hi QJ,

My question is if the test option "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is for fault injection as same as that you mentioned above? They both allow a fault to be inserted using the FAULT_INS field. But this fault belongs to STC controller itself, not CPU core fault. Right?

If yes, what's the meaning of this fault injection? In other words, how to discover the actual fault? Is there ESM error interrupt to response to the fault if it really happen?

Hi QJ,

Test option "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is just used to insert STC controller fault.

How to get the actual fault when STC controller can not work normally? By ESM interrupt or polling test? If by polling test, what's the test option?

If by polling test, what's the test option for STC controller selftest? After all, "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is just for fault injection.

Hi QJ,

1. Do you mean the error forcing test by using "SL_SelfTest_STC" with paramater "STC1_COMPARE_SELFCHECK" is a simulation of failure for normal LBIST test by using "SL_SelfTest_STC" with parameter "STC1_RUN"?

2. How to do fault injection mannually to trigger the faults that can be detected by polling test with funtion SL_SelfTest_PBIST?

I know there're lots of different algorithms within real tests. Can you provide just one example?

shenruming said:

1. Do you mean the error forcing test by using "SL_SelfTest_STC" with paramater "STC1_COMPARE_SELFCHECK" is a simulation of failure for normal LBIST test by using "SL_SelfTest_STC" with parameter "STC1_RUN"?

STC controller selftest (with parameter "STC1_RUN") is test the STC controller, and the test should PASS if STC is good. 

The STC controller self-check (with paramater "STC1_COMPARE_SELFCHECK") is to test STC controller with injected fault. The test should FAIL if STC is good. 

shenruming said:

2. How to do fault injection mannually to trigger the faults that can be detected by polling test with funtion SL_SelfTest_PBIST?

You can use algorithm "March13N" to RAM group 1-4 (ROM). The test will fail.

Hi QJ,

After I set "sl_stcREG->STCSCSCR" into "0x1A", the register "sl_stcREG->STCGSTAT" bit0 and bit1 did not turn to be "1" at all.

How to achieve it? Thanks.

How to get CPU reset? Reset manually or run some command automatically?