• State TI Thinks Resolved
  • Locked Locked
  • Replies 23 replies
  • Answers 8 answers
  • Subscribers 31 subscribers
  • Views 625 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM57L843: How to do fault injection for PBIST and LBIST

shenruming
Intellectual 575 points
Part Number: RM57L843

Now we need to use diagnostic libraries to do MCU selftest. How to add fault injection into PBIST/LBIST functions SL_SelfTest_PBIST/SL_SelfTest_STC?

  • 0
    TI__Guru 63235 points

    Hi Shenruming,

    Started working on your issue and we will get back to you on this soon.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 575 points

    Hi Jagadish,

    As you replied in email, "self-test fault injection may only be done by modifying CCMUYR = 0x9U in functions such as ccmSelfCheck". But we can't find the function "ccmSelfCheck" and set "CCMUYR = 0x9U".

    Can't we just use SafetTI Diagnostic Library to inject fault into functions "SL_SelfTest_PBIST/SL_SelfTest_STC"?

     

  • 0 in reply to jagadish gundavarapu
    Intellectual 575 points

    Hello Jagadish,

    Any update for this topic?

  • 0 in reply to shenruming
    TI__Guru 63235 points

    Apologies for the delay.

    Reassigned to QJ.

  • 0 in reply to jagadish gundavarapu
    TI__Guru**** 193286 points

    The LBIST and PBIST don't have fault injection. 

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ,

    Do we have any method to force the errors which can be detected by functions SL_SelfTest_PBIST and SL_SelfTest_STC?

    For C2000, there're detailed introduction of HWBIST/MBIST in specialized documents as below:

    Are there similar documents about LBIST/PBIST test for RM57L843 device?

    Thanks so much!

  • 0 in reply to shenruming
    TI__Guru**** 193286 points
    shenruming said:
    Do we have any method to force the errors which can be detected by functions SL_SelfTest_PBIST and SL_SelfTest_STC?

    It is possible to configure the PBIST logic by selecting an algorithm that should fail, and seeing if the PBIST Logic reports an error under this condition. For example, a read-write test could be performed on a read-only memory to ensure that a failure is reported. 

    You can enable the self-check feature of STC.

    shenruming said:
    Are there similar documents about LBIST/PBIST test for RM57L843 device?

    The TRM has detailed description. 

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ,

    It seems that setting FAULT_INS field of STCSCSCR register is equal to selecting the test type "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" for function SL_SelfTest_STC.

    If so, why did you say "The LBIST and PBIST don't have fault injection"?

  • 0 in reply to shenruming
    TI__Guru**** 193286 points

    CPU selftest is not exactly same as STC self-check. STC is a controller to test CPU core using LBIST controller which is implemented on the CPU.

    STC self-check is to check the STC rather than LBIST. 

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ,

    My question is if the test option "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is for fault injection as same as that you mentioned above? They both allow a fault to be inserted using the FAULT_INS field. But this fault belongs to STC controller itself, not CPU core fault. Right?

    If yes, what's the meaning of this fault injection? In other words, how to discover the actual fault? Is there ESM error interrupt to response to the fault if it really happen?

  • 0 in reply to shenruming
    TI__Guru**** 193286 points
    shenruming said:
    My question is if the test option "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is for fault injection as same as that you mentioned above?

    Yes, same

    shenruming said:
    They both allow a fault to be inserted using the FAULT_INS field. But this fault belongs to STC controller itself, not CPU core fault. Right?

    Yes, it is for STC self-check.

    shenruming said:
    If yes, what's the meaning of this fault injection?

    Yes. Please refer to 10.10 Self-Test Controller Diagnostics of device TRM.

    https://www.ti.com/lit/ug/spnu563a/spnu563a.pdf

    shenruming said:
    Is there ESM error interrupt to response to the fault if it really happen?

    On the completion of self-test, TEST_FAIL bit will be set in the STCGSTAT register.

    10.8.6 Self-Test Global Status Register (STCGSTAT)

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ,

    Test option "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is just used to insert STC controller fault.

    How to get the actual fault when STC controller can not work normally? By ESM interrupt or polling test? If by polling test, what's the test option?

  • 0 in reply to shenruming
    TI__Guru**** 193286 points
    shenruming said:
    How to get the actual fault when STC controller can not work normally? By ESM interrupt or polling test? If by polling test, what's the test option?

    TEST_FAIL is expected. If TEST_FAIL is not set, this means that the STC controller doesn't work normally. 

    There is no ESM flag for STC selfcheck. 

  • 0 in reply to QJ Wang
    Intellectual 575 points

    If by polling test, what's the test option for STC controller selftest? After all, "STC1_COMPARE_SELFCHECK/STC2_COMPARE_SELFCHECK" is just for fault injection.

  • 0 in reply to shenruming
    TI__Guru**** 193286 points

    STC controller selftest is different from STC controller selftcheck. You are correct that the STC controller selftcheck is selftest with fault injection. 

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ,

    1. Do you mean the error forcing test by using "SL_SelfTest_STC" with paramater "STC1_COMPARE_SELFCHECK" is a simulation of failure for normal LBIST test by using "SL_SelfTest_STC" with parameter "STC1_RUN"?

    2. How to do fault injection mannually to trigger the faults that can be detected by polling test with funtion SL_SelfTest_PBIST?

    I know there're lots of different algorithms within real tests. Can you provide just one example?

  • 0 in reply to shenruming
    TI__Guru**** 193286 points
    shenruming said:
    1. Do you mean the error forcing test by using "SL_SelfTest_STC" with paramater "STC1_COMPARE_SELFCHECK" is a simulation of failure for normal LBIST test by using "SL_SelfTest_STC" with parameter "STC1_RUN"?

    STC controller selftest (with parameter "STC1_RUN") is test the STC controller, and the test should PASS if STC is good. 

    The STC controller self-check (with paramater "STC1_COMPARE_SELFCHECK") is to test STC controller with injected fault. The test should FAIL if STC is good. 

  • 0 in reply to shenruming
    TI__Guru**** 193286 points
    shenruming said:
    2. How to do fault injection mannually to trigger the faults that can be detected by polling test with funtion SL_SelfTest_PBIST?

    You can use algorithm "March13N" to RAM group 1-4 (ROM). The test will fail.

  • 0 in reply to QJ Wang
    TI__Guru**** 193286 points

    The RAM Group 1~4 are read-only memory. The March13N will write/read data to memory. 

  • 0 in reply to QJ Wang
    Intellectual 575 points

    Hi QJ,

    After I set "sl_stcREG->STCSCSCR" into "0x1A", the register "sl_stcREG->STCGSTAT" bit0 and bit1 did not turn to be "1" at all.

    How to achieve it? Thanks.

  • 0 in reply to shenruming
    TI__Guru**** 193286 points

    The test is triggered after the CPU is taken to idle mode by executing the CPU Idle Instruction asm(“ WFI”). STC generates a CPU reset after completion of each test regardless of pass or fail.

    Did you get CPU reset? I call SDL API, and it always works.

  • 0 in reply to QJ Wang
    Intellectual 575 points

    How to get CPU reset? Reset manually or run some command automatically?

  • 0 in reply to shenruming
    TI__Guru**** 193286 points

    At the end of a CPU self-test or STC sel-check, the STC controller will reset the CPU.