RM42L432: RM42L432: Inject 1-bit error and 2-bit error into primary SRAM, but the result is not expected when inject 2-bit error.

Recently, I test Data ECC logic of primary SRAM of RM42L432. And I use HalCoGen +IAR Embedded Workbench for ARM.  

I use the data abort function "exception hanlders.c" from TI Safe Diagnostci library v 2.3.1.

1. Inject 1-bit error by modify the data of SRAM:

_coreEnableRamEcc_();
volatile uint64 sramEccTest[2]= {0xA0,0x10};
uint64 readram1,readram2;
_coreDisableRamEcc_();
sramEccTest[0]= 0xA1;
sramEccTest[1]= 0x11;
_coreEnableRamEcc_();
readram1=sramEccTest[0];
readram2=sramEccTest[1];

The result: (1)register RAMERRSTATUS: SERR=1; (2) ESMSR1=0x14000000

2. Inject 1-bit error by modify the ECC data:

_coreEnableRamEcc_();
volatile uint64 sramEccTest[2]= {0xA0,0x10};
uint64 readram1,readram2;
volatile uint64* eccB1,eccB2;

eccB1 = &sramEccTestBuff[0];
eccB1 = eccB1 + (0x00400000u/sizeof(uint64));

eccB2 = &sramEccTestBuff[1];
eccB2 = eccB2 + (0x00400000u/sizeof(uint64));

BIT_SET(sl_tcram1REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);/*Enable write ECC*/
BIT_SET(sl_tcram2REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);/*Enable write ECC*/

*eccB1 ^=0x01;
*eccB2 ^=0x01;

BIT_SET(sl_tcram1REG->RAMCTRL, TCRAM_RAMCTRL_ECCWRDIS);/*Disable write ECC*/
BIT_SET(sl_tcram2REG->RAMCTRL, TCRAM_RAMCTRL_ECCWRDIS);/*Disable write ECC*/

readram1=sramEccTest[0];
readram2=sramEccTest[1];

The result: (1)register RAMERRSTATUS: SERR=1; (2) ESMSR1=0x14000000

3. Inject 2-bit error by modify the data of SRAM:

_coreEnableRamEcc_();
volatile uint64 sramEccTest[2]= {0xA0,0x10};
uint64 readram1,readram2;
_coreDisableRamEcc_();
sramEccTest[0]= 0xB1;
sramEccTest[1]= 0x21;
_coreEnableRamEcc_();
readram1=sramEccTest[0];
readram2=sramEccTest[1];

The result: (1)register RAMERRSTATUS: DERR=0 ; (2) ESMSR3=0x00000000
That's not the expected result!

4. Inject 2-bit error by modify the ECC data:

_coreEnableRamEcc_();
volatile uint64 sramEccTest[2]= {0xA0,0x10};
uint64 readram1,readram2;
volatile uint64* eccB1,eccB2;

eccB1 = &sramEccTestBuff[0];
eccB1 = eccB1 + (0x00400000u/sizeof(uint64));

eccB2 = &sramEccTestBuff[1];
eccB2 = eccB2 + (0x00400000u/sizeof(uint64));

BIT_SET(sl_tcram1REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);/*Enable write ECC*/
BIT_SET(sl_tcram2REG->RAMCTRL, TCRAM_RAMCTRL_ECCWREN);/*Enable write ECC*/

*eccB1 ^=0x03;
*eccB2 ^=0x03;

BIT_SET(sl_tcram1REG->RAMCTRL, TCRAM_RAMCTRL_ECCWRDIS);/*Disable write ECC*/
BIT_SET(sl_tcram2REG->RAMCTRL, TCRAM_RAMCTRL_ECCWRDIS);/*Disable write ECC*/

readram1=sramEccTest[0];
readram2=sramEccTest[1];

The result: (1)register RAMERRSTATUS: DERR=1 ; (2) ESMSR3=0x28;

My question:
(1) Why "Inject 2-bit error by modify the data of SRAM" does not get the expected result? 
(2) How to correct my code to get the expected result?

Thank you.