TMS570LS1224: What is the functionality of MPMODE bit in SYSESR

Part Number: TMS570LS1224

Dear Hercules Team,

the meaning of bit 0 (MPMODE) in the system exception status register (SYSESR) is not clear, According to the TRM MPMODE "... indicates the current memory protection unit (MPU) mode.". In the CPU reset control register (CPURSTCR) following is mentioned: "The CPURSTCR register shown in Figure 2-47 and described in Table 2-61, allows the memory protection mode to be configured. ...", although neither the figure nor the table include a corresponding bit.

Could you please provide feedback to following questions:

1. What is the meaning of SYSESR.MPMODE?
2. Is SYSESR.MPMODE impacted by the M bit (MPU enable) of the Cortex-R4 system control register (CP15)?
3. Why does the description of CPURSTCR refer to memory protection mode?

Thanks,
Peter.

P.S.: I picked an exemplary part number. I checked multiple devices from the Hercules family and all corresponding TRMs incorporate the same descriptions regarding SYSESR and CPURSTCR.