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RTOS/TM4C1233H6PM: Intermittent Default ISR Handler Call

Peyton Davari

Expert 1180 points

Part Number: TM4C1233H6PM

Tool/software: TI-RTOS

It's a very consistent every other time I compile and debug that I run into the problem where the IntDefaultHandler function is called.

First Run: Timers Trigger interrupts as expected

Second Run: IntDefaulHandler is called

Third Run: Timers Trigger Interrupts as expected

Fourth Run: IntDefaultHandler is called

I'm not sure what could cause this behavior but it doesn't begin happening until I had a fourth and fifth timer interrupt. Here is the code that I am seeing the above stated problems with:

    ///**************************************************************************************
    // * Setup TIMERS
    // ***************************************************************************************/

    //Enable processor interrupts.
    IntMasterEnable();

    //Enable peripheral TIMER0
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER2);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER3);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER4);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER5);

    //Configure Timers to be split for two 16-bit periodic timers
    TimerConfigure(TIMER0_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
    TimerConfigure(TIMER1_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
    TimerConfigure(TIMER2_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
    TimerConfigure(TIMER3_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
    TimerConfigure(TIMER4_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);
    TimerConfigure(TIMER5_BASE, TIMER_CFG_SPLIT_PAIR | TIMER_CFG_A_PERIODIC | TIMER_CFG_B_PERIODIC);

    //Enable Wait For Trigger
    //TimerControlWaitOnTrigger(TIMER0_BASE, TIMER_B, true);

    //Set Time Delays for Periodic Timers
    TimerLoadSet(TIMER0_BASE, TIMER_A, 13000);
    TimerLoadSet(TIMER0_BASE, TIMER_B, 10000);   // 0.5 SEC

    //Set Time Delays for Periodic Timers
    TimerLoadSet(TIMER1_BASE, TIMER_A, 7000);
    TimerLoadSet(TIMER1_BASE, TIMER_B, 4000);   // 0.5 SEC

    //Set Time Delays for Periodic Timers
    TimerLoadSet(TIMER2_BASE, TIMER_A, 8000);
    TimerLoadSet(TIMER2_BASE, TIMER_B, 5000);   // 0.5 SEC

    //Set Time Delays for Periodic Timers
    TimerLoadSet(TIMER3_BASE, TIMER_A, 13000);
    TimerLoadSet(TIMER3_BASE, TIMER_B, 10000);   // 0.5 SEC

    //Set Time Delays for Periodic Timers
    TimerLoadSet(TIMER4_BASE, TIMER_A, 7000);
    TimerLoadSet(TIMER4_BASE, TIMER_B, 4000);   // 0.5 SEC

    //Set Time Delays for Periodic Timers
    TimerLoadSet(TIMER5_BASE, TIMER_A, 8000);
    TimerLoadSet(TIMER5_BASE, TIMER_B, 5000);   // 0.5 SEC


    //Enable the TIMER0A AND TIMER0B interrupt on the processor (NVIC).
    IntEnable(INT_TIMER0A);
    IntEnable(INT_TIMER0B);

    IntEnable(INT_TIMER1A);
    IntEnable(INT_TIMER1B);

    IntEnable(INT_TIMER2A);
    IntEnable(INT_TIMER2B);

    IntEnable(INT_TIMER3A);
    IntEnable(INT_TIMER3B);

    IntEnable(INT_TIMER4A);
    IntEnable(INT_TIMER4B);

    IntEnable(INT_TIMER5A);
    IntEnable(INT_TIMER5B);

    //Register Timer Interrupts
    TimerIntRegister(TIMER0_BASE, TIMER_A, Timer0AIntHandler);
    TimerIntRegister(TIMER0_BASE, TIMER_B, Timer0BIntHandler);

    TimerIntRegister(TIMER1_BASE, TIMER_A, Timer1AIntHandler);
    TimerIntRegister(TIMER1_BASE, TIMER_B, Timer1BIntHandler);

    TimerIntRegister(TIMER2_BASE, TIMER_A, Timer2AIntHandler);
    TimerIntRegister(TIMER2_BASE, TIMER_B, Timer2BIntHandler);

    TimerIntRegister(TIMER3_BASE, TIMER_A, Timer3AIntHandler);
    TimerIntRegister(TIMER3_BASE, TIMER_B, Timer3BIntHandler);

    TimerIntRegister(TIMER4_BASE, TIMER_A, Timer4AIntHandler);
    TimerIntRegister(TIMER4_BASE, TIMER_B, Timer4BIntHandler);

    TimerIntRegister(TIMER5_BASE, TIMER_A, Timer5AIntHandler);
    TimerIntRegister(TIMER5_BASE, TIMER_B, Timer5BIntHandler);

    //Enable Timer Interrupts
    TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
    TimerIntEnable(TIMER0_BASE, TIMER_TIMB_TIMEOUT);

    TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
    TimerIntEnable(TIMER1_BASE, TIMER_TIMB_TIMEOUT);

    TimerIntEnable(TIMER2_BASE, TIMER_TIMA_TIMEOUT);
    TimerIntEnable(TIMER2_BASE, TIMER_TIMB_TIMEOUT);

    TimerIntEnable(TIMER3_BASE, TIMER_TIMA_TIMEOUT);
    TimerIntEnable(TIMER3_BASE, TIMER_TIMB_TIMEOUT);

    TimerIntEnable(TIMER4_BASE, TIMER_TIMA_TIMEOUT);
    TimerIntEnable(TIMER4_BASE, TIMER_TIMB_TIMEOUT);

    TimerIntEnable(TIMER5_BASE, TIMER_TIMA_TIMEOUT);
    TimerIntEnable(TIMER5_BASE, TIMER_TIMB_TIMEOUT);

    //Enable Timers
    TimerEnable(TIMER0_BASE, TIMER_A);

Any suggestion as to what could be causing this behavior would be appreciated, thanks!

Peyton

over 8 years ago

0 ToddMullanix over 8 years ago

TI__Guru* 96960 points

Are you using TI-RTOS (or SYS/BIOS...which is the TI-RTOS kernel) or just using driverlib in TivaWare?

0 Peyton Davari over 8 years ago in reply to ToddMullanix

Expert 1180 points

Good catch, sorry about that. I am just using the TivaWare driverlib

0 ToddMullanix over 8 years ago in reply to Peyton Davari

TI__Guru* 96960 points

No problem. I'll move the the thread to the TM4C forum.

0 Chester Gillon over 8 years ago

Guru 92251 points

Peyton Davari said:
I'm not sure what could cause this behavior but it doesn't begin happening until I had a fourth and fifth timer interrupt. Here is the code that I am seeing the above stated problems with

Assuming that you are using CCS to perform the debugging, I think what is happening is that by default CCS doesn't perform a System Reset of the Tiva device when starting a debug session. That means that after a debug session is started the timer peripherals are still enabled for interrupt generation from the previous run. Since TimerIntRegister() is used in the code to register the interrupt handlers there is a race condition where the timer peripheral which remains configured for interrupt generation from the previous debug session can generate an interrupt before the TimerIntRegister() has been called, resulting in the default interrupt handler being called.

The Default Interrupt Handler section in the Diagnosing Software Faults in Stellaris® Microcontrollers could be used to confirm if one of the timer interrupts resulted in the default interrupt handler being called.

Under the CCS project properties there are options you can set to perform a reset during a download which should reset all peripgerals, under both:

- Debug -> Program/Memory Load Options -> Connection Options -> Reset the target on a connect

- Debug -> Flash Settings -> Flash Settings -> Reset target during program load to Flash memory

Try setting those options to reset the target.

Note that there is a bug in CCS 7.0 and CCS 7.1 where attempting to set the "Reset the target on a connect" and "Reset target during program load to Flash memory" options has no effect (https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/589281). A work-around is to the add the following to the GEL script for the device:

OnPreFileLoaded()
{
    GEL_AdvancedReset ("System Reset");
}