Hi,
I am currently checking the CPU behaviour in various conditions of SEU and MEU errors in RAM.
1) First, I want to make a reference to an other post, in which I think there is a mistake: https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/630389
For the third point of the original question of this post, the answer is that ECC generation is not disabled when setting ECC DETECT EN field of RAMCTRL register to 0x5.
With the testing performed recently, I would say that this is wrong. Here is the test procedure:
- set ECC_DETECT_EN to 0xA (enable ECC)
- auto-initialize internal RAM to 0 (ECC codes are updated)
- write 32 bits at address 0x0800_0000 with value 0x4
- read corresponding 8-bit ECC value at address 0x0840_0000: value is 0xEA
- set ECC_DETECT_EN to 0x5 (disable ECC)
- write 32 bits at address 0x0800_0000 with value 0x5
- read corresponding 8-bit ECC value at address 0x0840_0000: value is 0xEA
>> ECC memory reads are identical
Same test with letting the ECC enabled in RAM:
- set ECC_DETECT_EN to 0xA (enable ECC)
- auto-initialize internal RAM to 0 (ECC codes are updated)
- write 32 bits at address 0x0800_0000 with value 0x4
- read corresponding 8-bit ECC value at address 0x0840_0000: value is 0xEA
- write 32 bits at address 0x0800_0000 with value 0x5
- read corresponding 8-bit ECC value at address 0x0840_0000: value is 0x03
>> ECC memory reads are different due to ECC enabling and different values written
To avoid confusion, I recommend to add this point to the original post, or invalidate the given answer.
2) According to Table 8-1 of TMS570LC4357 TRM, the L2RAMW is supposed to generate a bus error when a double-bit Read-Modify-Write (RMW) error is detected during sub-64bits write by the cortex-r5f.
Thanks to point 1) being clarified, I was able to inject double-bit fault in RAM and perform a 16-bit write from the core to check this behaviour and I noticed the following:
- if the core MPU is disabled (using the default memory map documented in Cortex-R5 TRM Table 7-1) >> no abort is generated
- if the core MPU is enabled with one region for the RAM configured as DEVICE or NORMAL memory >> no abort is generated
- if the core MPU is enabled with one region for the RAM configured as STRONGLY-ORDERED memory >> a data abort is generated and the data fault is logged in the Cortex-R5 DFSR register.
- independently of the MPU confuguration, the ESM group 3 channel 3 is triggered as expected.
As far as I understand, the "bus error" documented in the TMS570LC4357 TRM is related to the Cortex-R5 TRM "External faults" documented in chapter "8.3.1 Faults > External Faults". Am I correct on this point?
By the following sentence "Non-exclusive stores to normal-type or device-type memory generate asynchronous aborts", I understand that when the MPU is configured as NORMAL or DEVICE memory for the RAM region, an asynchronous abort should be generated when executing a non-exclusive store, but even with a while loop after the 16-bit write to RAM is performed, the data abort is not generated.
This behaviour seems not consistent with the documentation. Could you clarify the normal and expected behaviour?
If this is a wrong behaviour, is it related to the errata "DEVICE#40" documented in Silicon B errata document?
Best regards,
Gael