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TMS570LC4357: Test of ECC L2RAMW

user5896989
Prodigy 220 points
Part Number: TMS570LC4357

Hello,

I would like to test ECC Mechanism of L2RAMMW.

I have seen the Diagnostic test procedure described in Technical reference Manual to test 1 or 2 bit in error.
In this case RAMERRSTATUS[22,21,20,19,12,11,10, 4] are checked for the test.

With an other procedure, is it possible to test the following Bit in RAMERRSTATUS register :
Bit0 : CPUWE (CPU Write Single Error)
Bit1 : REME (Read ECC Malfunction Error. Indicates that the SECDED logic failed to correct a single bit error on the read of a read-modify-write operation)
Bit3 : WEME (Write ECC Malfunction Error. This bit Indicates that the SECDED logic failed to correct a single bit error
during a CPU write operation)
Bit5 : CPUWDE (CPU Write Double-bit Error. This bit indicates that an ECC uncorrectable (double bit) error was detected during write access)
Bit7 : RMWDE (Read-Modify-Write Double Bit Error. This bit indicates that an ECC uncorrectable (double bit) error was
detected during read access of the read modify write operation)

Best regards,

François

  • 0
    TI__Guru**** 193266 points
    Hello François,

    The diagnostic test will only test the error listed by RAMERRSTATUS[22,21,20,19,12,11,10, 4] bits. RAMERRSTATUS[7,5,3,1,0] will not be triggered by the diagnostic test.
  • 0 in reply to QJ Wang
    Prodigy 220 points
    Hello Wang,

    Thank you for you answer, but I would like to know if it's possible to test ECC mechanism in functional configuration to check RAMERRSTATUS[0,1,3,5,7] without using the diagnostic test?
    For example, is it possible to deactivate ECC mechanism with ECC_DETEC_EN Bit (RAMCTRL register), modify 1 or 2 bit in RAM AREA and activate ECC_DETEC_EN? What's happen in this case.

    If no, can you confim me that Diagnostic test correctly covers all the functional mechanism of ECC (64 bit RAM Data and 8 Bit ECC)?

    Best regards,

    François
  • 0 in reply to user5896989
    TI__Guru**** 193266 points
    Hello François,

    If there is CPU write single/double-bit error, read/write ECC malfunction error, or read-modify-write error in normal memory access operations, the bit {0,1,3,5,7] of RAMERRSTATUS will be set. The diagnostic test covers the compare logic and SECDED in L2RAMW.