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RM48L952: prefetchEntry during checkRAMUERRTest()

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Hello there,

I am using HALCoGen generated code for the RM48L952, I am not using interrupts (they are disabled via _disable_interrupts_(), vim is also configured to not generate interrupts.
To check for errors I check esmREG->SR1[0..2], esmREG->SSR2 and the core cp15 registers (datafault, instructionfault..).
I want to run checkRAMUERRTest() generated by HALCoGen periodically.

When running without debugger connected (after PORST) this works fine.
However when I connect via JTAG a prefetchEntry interrupt is called at the end of the checkRAMUERRTest function. If I then restart (nRST) and re-run the program no prefetchEntry interrupt is generated.
In the prefetchEntry i read out the cp15 registers.

_coreGetInstructionFault_() returns 0xd indicating permission
_coreGetInstructionFaultAddress_() returns 0xe3cfefc6.

Any help on where or how to look for the instruction fault would be welcome.
Is this related to the MPU or CPU mode (sys, user, ..)?

Best regards,,

Karel

  • Hello Karel,

    It looks like the code is trying to access an unimplemented memory. The CCMR4 test required code execution without JTAG connected, but for SRAM and flash related test, the JTAG should not impact the test.

    Do you have breakpoints when you run the code? When JTAG is connected, when RUN option do you use, RUN (resume) or Free RUN?
  • Hey QJ,


    I am not performing the CCMR4 test.
    I am using GDB. I do have brakepoints set. I am performing checkRAMUERRTest() and checkRAMAddrParity() in _c_int00 before the call to main().
    Setting breakpoints or stepping (step/next) through the code or continue'ing (continue) does not seem to affect this.
  • Hello,

    I just did the same test, didn't see any problem. I did checkRAMAddrParity() after pbist test.