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TMS320F280039C: CLA and CPU arbitration

Joe Ji
Expert 3760 points
Part Number: TMS320F280039C

Hi Team

below are two questions for CLA and CPU memory access:

1. 0039C TRM 7.3.2 describes if CLA access to the same location that CPU is processing read-modify-write, the CLA write will be ignored, but if CLA requests "read", will the data before CPU write or data after CPU write can CLA read?

2. Same question as question 1 for Message RAM.

3. I compare 0049 TRM there is no the same description, what's the detail rule of 0049? 

Thanks and best regards

Joe

10th May

  • 0
    TI__Expert 3760 points

    for question 3 I think I found in TRM 5.3 corresponding chapter is 12.5 

  • 0 in reply to Joe Ji
    TI__Mastermind 18505 points

    Hi Joe,

    I have asked the design team about your first 2 questions and will get back to you when I get a response from them. 

    For your third question, yes, the arbitration scheme should be the same for the F28004x as well. Both devices use the same CLA module type.

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Mastermind 18505 points

    Hi Joe,

    After consulting with the design team, they confirmed that for both the peripheral shared memory and the message RAMs: if the CPU is performing a read-modify-write operation and the CLA tries to read the same memory in the middle of the operation (after the CPU read and before the CPU write), the CLA would read in the old data. In other words, if the CLA tries to read before the CPU write operation takes place, the memory won't have been updated yet so the CLA wouldn't see the new data.

    What is the customer's application in this case? I can ask design if their approach should have any issues. 

    Best Regards,

    Delaney

  • 0 in reply to Delaney Woodward
    TI__Expert 3760 points

    Hi Delaney

    Thanks for following up, below are the use cases:

    Sample data: 3 phase current,

    Calculation date: 3 phase PLL calculated by CPU,

    The the latest data should be updated to CLA, PLL data should align with Current sample data at one time point.

    R/W operation:

    1. SW define the region1: CPU R/W, CLA R 

    2. SW define the region2: CLA R/W, CPU R 

    2. Open region: CLA R/W, CPU R/W, SW design CLA W and CPU W won't happen at the same time.

     

    Question:

    1, How to ensure PLL data align with Current sample data at one time point?

    2. Does peripheral shared data means LSx RAM?

    Thanks and best regards

    Joe

    16th May

  • +1 in reply to Joe Ji
    TI__Mastermind 18505 points

    Hi Joe,

    Is my understanding of the application flow correct:

    1. The CLA code will read in the 3 phase current sample data and write it to the open region.

    2. The CPU code will read the 3 phase current sample data from the open region, do the 3 phase PLL calculation, and then overwrite the CLA calculation in the open region.

    Does the CLA need to use the data calculated by the CPU? Are you asking how these two operations can be synchronized with each other? I would suggest having some sort of synchronization flag in this case at a different spot in the shared memory. The CLA could set this flag when it has written new sample data to the shared memory, then the CPU could read the new data from the shared memory and clear the synch flag. The CLA would have to wait until the synch flag is cleared to write anymore new data. Let me know if this approach would work?

    Best Regards,

    Delaney