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Tool/software:
In my 3-phase SVPWM implementation, my dead-band waveform follows the Active high complementary mode (Figure 18-35 of sprui33h) with my rising edge delay (RED) equal to the falling edge delay (FED)
If my fixed delay value (RED or FED or both) cannot be achieved for a particular duty cycle during the SPVWM cycle, what will the PWM output look like?
Thanks
David Nyarko
Hi David,
Could you expand on why the RED/FED would not be able to be achieved? If you are initializing the EPWM with these settings, they should apply every cycle (unless this pattern is masked by some another PWM setting, for example, if you configure a trip that is forcing the PWM outputs high/low).
If there is no RED/FED, then the edges of your complementary EPWMs would be aligned with no dead time in between rising and falling edges.
Best Regards,
Allison
Hi Allison,
Sorry for not being clear. In the EPWM initialization routines, I set each of my 3 EPWMs to have a fixed deadband (for RED and FED).
For each EPWM cycle (ISR entry) , i calculate the required pulse width for each of the 3 phases base on a formula. I then determine the required compare register value to pass to each EPWM
If the compare register value (proportional to the computed pulse width ) which i pass to a particular EPWM module happens to be smaller than the deadband setting, does the processor pin output
a constant logic low for that cycle and for the complementary EPWM pin a logic high?
I hope this is making sense..
Thanks
Hi David,
To clarify, you are initializing with a fixed period, action qualifiers, and deadband etc. The only parameter changing is your counter compare value (the timing of your action qualifiers)?
Please review this related past thread to see if it resolves your inquiry (these two devices use the same EPWM type):
Best Regards,
Allison